Map TRACE Report

Loading design for application trce from file readanwrite_impl1_map.ncd.
Design name: Test
NCD version: 3.3
Vendor:      LATTICE
Device:      LFXP2-5E
Package:     TQFP144
Performance: 6
Loading device for application trce from file 'mg5a26x29.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.42.
Performance Hardware Data Status:   Final          Version 11.5.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.0.240.2
Thu Jul 14 12:50:26 2022

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -u 0 -gt -mapchkpnt 0 -sethld -o ReadAnWrite_impl1.tw1 -gui ReadAnWrite_impl1_map.ncd ReadAnWrite_impl1.prf 
Design file:     readanwrite_impl1_map.ncd
Preference file: readanwrite_impl1.prf
Device,speed:    LFXP2-5E,6
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

Preference Summary

FREQUENCY PORT "ipClk" 50.000000 MHz (0 errors)
            3430 items scored, 0 timing errors detected.
Report:  138.370MHz is the maximum frequency for this preference.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers_Resetio" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets_UART_INST_opTxio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
            0 items scored.

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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opTxWrEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/edgeDetector[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/reset" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opTxReady" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.SoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.EoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxSend" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData_tri_enable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opTxBusy" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxValid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/clockEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers_Resetio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets_UART_INST_opTxio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
            0 items scored.

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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opTxWrEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/edgeDetector[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opTxReady" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.SoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.EoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxSend" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData_tri_enable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opTxBusy" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxValid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[9]" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/clockEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers_Resetio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[3]" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets_UART_INST_opTxio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opTxWrEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/edgeDetector[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opTxReady" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.SoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.EoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxSend" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData_tri_enable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opTxBusy" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxValid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/clockEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets_UART_INST_edgeDetectorio[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets_UART_INST_edgeDetectorio[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers_Resetio" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers_Resetio" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets_UART_INST_opTxio" TO PORT "opTx" (0 errors)
            1 item scored.

BLOCK PATH FROM CELL "uartPackets_UART_INST_opTxio" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLEDs[7]" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opTx" (0 errors)
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BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/state[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/state[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opTxWrEnable" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opTxWrEnable" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/state[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/state[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Valid" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Valid" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/edgeDetector[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/edgeDetector[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/edgeDetector[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/edgeDetector[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[7]" TO PORT "opLEDs[7]" (0 errors)
            1 item scored.

BLOCK PATH FROM CELL "registers/opRdData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/reset" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/reset" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opTxReady" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opTxReady" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Valid" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Valid" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.SoP" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.SoP" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.EoP" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.EoP" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxSend" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxSend" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData_tri_enable" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData_tri_enable" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txState[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txState[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/reset" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/reset" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opTxBusy" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opTxBusy" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxValid" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxValid" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/edgeDetector[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/edgeDetector[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/clockEnable" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/clockEnable" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

Unconstrained: CLOCK_DOMAIN
            3108 unconstrained paths found

Unconstrained: INPUT_SETUP
            3 unconstrained paths found

Unconstrained: CLOCK_TO_OUT
            7 unconstrained paths found

Unconstrained: MAXDELAY
            0 unconstrained paths found

BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "ipClk" 50.000000 MHz ;
            3430 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 12.773ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]  (from ipClk_c +)
   Destination:    FF         Data in        Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]  (to ipClk_c +)

   Delay:               7.001ns  (22.2% logic, 77.8% route), 6 logic levels.

 Constraint Details:

      7.001ns physical path delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509 meets
     20.000ns delay constraint less
      0.226ns CE_SET requirement (totaling 19.774ns) by 12.773ns

 Physical Path Details:

      Data path Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         5   e 0.908 */SLICE_103.Q0 to */SLICE_628.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.238 */SLICE_628.A0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_502.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_502.A0 to */SLICE_502.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_502
ROUTE         3   e 0.908 */SLICE_502.F0 to */SLICE_508.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_tu[0]
CTOF_DEL    ---     0.238 */SLICE_508.C0 to */SLICE_508.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/SLICE_508
ROUTE         1   e 0.908 */SLICE_508.F0 to */SLICE_509.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]_0_sqmuxa (to ipClk_c)
                  --------
                    7.001   (22.2% logic, 77.8% route), 6 logic levels.

Report:  138.370MHz is the maximum frequency for this preference.


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers_Resetio" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipReset
   Destination:    FF         Data in        registers_Resetio  (to ipClk_c +)

   Delay:               1.721ns  (47.2% logic, 52.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813         19.PAD to       19.PADDI ipReset
ROUTE         3   e 0.908       19.PADDI to *eset_MGIOL.DI ipReset_c (to ipClk_c)
                  --------
                    1.721   (47.2% logic, 52.8% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets_UART_INST_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipReset
   Destination:    FF         Data in        Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]  (to ipClk_c +)

   Delay:               1.721ns  (47.2% logic, 52.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813         19.PAD to       19.PADDI ipReset
ROUTE         3   e 0.908       19.PADDI to */SLICE_299.M1 ipReset_c (to ipClk_c)
                  --------
                    1.721   (47.2% logic, 52.8% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opTxWrEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/edgeDetector[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/reset" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipReset
   Destination:    FF         Data in        uartPackets/reset  (to ipClk_c +)

   Delay:               1.721ns  (47.2% logic, 52.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813         19.PAD to       19.PADDI ipReset
ROUTE         3   e 0.908       19.PADDI to */SLICE_437.M0 ipReset_c (to ipClk_c)
                  --------
                    1.721   (47.2% logic, 52.8% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opTxReady" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.SoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.EoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData_tri_enable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/clockEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipRx
   Destination:    FF         Data in        uartPackets_UART_INST_edgeDetectorio[0]  (to ipClk_c +)

   Delay:               1.721ns  (47.2% logic, 52.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813        110.PAD to      110.PADDI ipRx
ROUTE         2   e 0.908      110.PADDI to  ipRx_MGIOL.DI ipRx_c (to ipClk_c)
                  --------
                    1.721   (47.2% logic, 52.8% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers_Resetio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets_UART_INST_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opTxWrEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/edgeDetector[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opTxReady" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.SoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.EoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData_tri_enable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[9]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipRx
   Destination:    FF         Data in        uartPackets/UART_INST/localRxData[9]  (to ipClk_c +)

   Delay:               1.960ns  (53.6% logic, 46.4% route), 2 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813        110.PAD to      110.PADDI ipRx
ROUTE         2   e 0.908      110.PADDI to */SLICE_393.A1 ipRx_c
CTOF_DEL    ---     0.238 */SLICE_393.A1 to */SLICE_393.F1 uartPackets/UART_INST/SLICE_393
ROUTE         1   e 0.001 */SLICE_393.F1 to *SLICE_393.DI1 uartPackets/UART_INST/localRxData_5[9] (to ipClk_c)
                  --------
                    1.960   (53.6% logic, 46.4% route), 2 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/clockEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers_Resetio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[3]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipButtons[3]
   Destination:    FF         Data in        readRegisters.Buttons_0io[3]  (to ipClk_c +)

   Delay:               1.721ns  (47.2% logic, 52.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813         54.PAD to       54.PADDI ipButtons[3]
ROUTE         1   e 0.908       54.PADDI to *s[3]_MGIOL.DI ipButtons_c[3] (to ipClk_c)
                  --------
                    1.721   (47.2% logic, 52.8% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets_UART_INST_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opTxWrEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/edgeDetector[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opTxReady" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.SoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.EoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData_tri_enable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/clockEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets_UART_INST_edgeDetectorio[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets_UART_INST_edgeDetectorio[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers_Resetio" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers_Resetio" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets_UART_INST_opTxio" TO PORT "opTx" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              uartPackets_UART_INST_opTxio  (from ipClk_c +)
   Destination:    Port       Pad            opTx

   Delay:               3.171ns  (71.4% logic, 28.6% route), 2 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
C2OUT_DEL   ---     1.367 opTx_MGIOL.CLK to *x_MGIOL.IOLDO opTx_MGIOL (from ipClk_c)
ROUTE         1   e 0.908 *x_MGIOL.IOLDO to      109.IOLDO opTx_c
DOPAD_DEL   ---     0.896      109.IOLDO to        109.PAD opTx
                  --------
                    3.171   (71.4% logic, 28.6% route), 2 logic levels.


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets_UART_INST_opTxio" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/state[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/state[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opTxWrEnable" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opTxWrEnable" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/state[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/state[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Valid" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Valid" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/edgeDetector[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/edgeDetector[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/edgeDetector[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/edgeDetector[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[7]" TO PORT "opLEDs[7]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              registers/opWrRegisters.LEDs[7]  (from ipClk_c +)
   Destination:    Port       Pad            opLEDs[7]

   Delay:               2.388ns  (62.0% logic, 38.0% route), 2 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_346.CLK to */SLICE_346.Q1 registers/SLICE_346 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_346.Q1 to       37.PADDO opLEDs_c[7]
DOPAD_DEL   ---     1.117       37.PADDO to         37.PAD opLEDs[7]
                  --------
                    2.388   (62.0% logic, 38.0% route), 2 logic levels.


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/reset" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/reset" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opTxReady" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opTxReady" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Valid" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Valid" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.SoP" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.SoP" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.EoP" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.EoP" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxSend" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxSend" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData_tri_enable" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData_tri_enable" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txState[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txState[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/reset" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/reset" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opTxBusy" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opTxBusy" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxValid" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxValid" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/edgeDetector[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/edgeDetector[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/clockEnable" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/clockEnable" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: Unconstrained: CLOCK_DOMAIN
            3108 unconstrained paths found
--------------------------------------------------------------------------------

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.938ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_283 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.861ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_283.CLK to */SLICE_283.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_283 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_283.Q0 to */SLICE_531.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]
CTOF_DEL    ---     0.238 */SLICE_531.C0 to */SLICE_531.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.232 */SLICE_531.F0 to */SLICE_531.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_531.C1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.861   (25.6% logic, 74.4% route), 9 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.938ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.861ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_531.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_531.A0 to */SLICE_531.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.232 */SLICE_531.F0 to */SLICE_531.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_531.C1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.861   (25.6% logic, 74.4% route), 9 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.938ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_278 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.861ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_278.CLK to */SLICE_278.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_278 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_278.Q0 to */SLICE_531.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]
CTOF_DEL    ---     0.238 */SLICE_531.B0 to */SLICE_531.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.232 */SLICE_531.F0 to */SLICE_531.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_531.C1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.861   (25.6% logic, 74.4% route), 9 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.468ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.391ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_642.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_642.A0 to */SLICE_642.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         4   e 0.908 */SLICE_642.F0 to */SLICE_509.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_1
CTOF_DEL    ---     0.238 */SLICE_509.B1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.391   (24.2% logic, 75.8% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.468ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_301 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.391ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_301.CLK to */SLICE_301.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_301 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_301.Q0 to */SLICE_661.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]
CTOF_DEL    ---     0.238 */SLICE_661.C0 to */SLICE_661.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661
ROUTE         1   e 0.908 */SLICE_661.F0 to */SLICE_509.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][0]
CTOF_DEL    ---     0.238 */SLICE_509.D1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.391   (24.2% logic, 75.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.468ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.391ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to */SLICE_661.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_661.A0 to */SLICE_661.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661
ROUTE         1   e 0.908 */SLICE_661.F0 to */SLICE_509.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][0]
CTOF_DEL    ---     0.238 */SLICE_509.D1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.391   (24.2% logic, 75.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.468ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.391ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_531.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_531.B1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.391   (24.2% logic, 75.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.468ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.391ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_531.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_531.A1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.391   (24.2% logic, 75.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.468ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.391ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_534.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_534.B0 to */SLICE_534.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_534
ROUTE         4   e 0.908 */SLICE_534.F0 to */SLICE_509.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_0
CTOF_DEL    ---     0.238 */SLICE_509.A1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.391   (24.2% logic, 75.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.468ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.391ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_642.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_642.B0 to */SLICE_642.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         4   e 0.908 */SLICE_642.F0 to */SLICE_509.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_1
CTOF_DEL    ---     0.238 */SLICE_509.B1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.391   (24.2% logic, 75.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.468ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.391ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_534.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_534.A0 to */SLICE_534.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_534
ROUTE         4   e 0.908 */SLICE_534.F0 to */SLICE_509.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_0
CTOF_DEL    ---     0.238 */SLICE_509.A1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.391   (24.2% logic, 75.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.373ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (8.147ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_615.Q0 to */SLICE_721.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_721.B0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    8.147   (22.0% logic, 78.0% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.373ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (8.147ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         5   e 0.908 */SLICE_103.Q0 to */SLICE_628.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.238 */SLICE_628.A0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    8.147   (22.0% logic, 78.0% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.373ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (8.147ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_721.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_721.A0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    8.147   (22.0% logic, 78.0% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.373ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (8.147ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_721.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_721.C0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    8.147   (22.0% logic, 78.0% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.373ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (8.147ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_721.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_721.D0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    8.147   (22.0% logic, 78.0% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    8.373ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (8.147ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_103.Q1 to */SLICE_628.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]
CTOF_DEL    ---     0.238 */SLICE_628.B0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    8.147   (22.0% logic, 78.0% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.262ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.185ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         4   e 0.908 *u/SLICE_50.Q0 to */SLICE_626.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_626.B0 to */SLICE_626.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_626
ROUTE         1   e 0.908 */SLICE_626.F0 to */SLICE_482.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_8_2
CTOF_DEL    ---     0.238 */SLICE_482.B0 to */SLICE_482.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.232 */SLICE_482.F0 to */SLICE_482.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_0_o5_1_1
CTOF_DEL    ---     0.238 */SLICE_482.B1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.185   (27.8% logic, 72.2% route), 9 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    8.262ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (8.185ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_51.CLK to *u/SLICE_51.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (from jtaghub16_jtck)
ROUTE         4   e 0.908 *u/SLICE_51.Q1 to */SLICE_626.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_626.A0 to */SLICE_626.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_626
ROUTE         1   e 0.908 */SLICE_626.F0 to */SLICE_482.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_8_2
CTOF_DEL    ---     0.238 */SLICE_482.B0 to */SLICE_482.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.232 */SLICE_482.F0 to */SLICE_482.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_0_o5_1_1
CTOF_DEL    ---     0.238 */SLICE_482.B1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    8.185   (27.8% logic, 72.2% route), 9 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_49.Q0 to */SLICE_565.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_565.B0 to */SLICE_565.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_565
ROUTE         2   e 0.908 */SLICE_565.F0 to */SLICE_482.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_8_3
CTOF_DEL    ---     0.238 */SLICE_482.C1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_50.Q1 to */SLICE_565.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_565.A0 to */SLICE_565.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_565
ROUTE         2   e 0.908 */SLICE_565.F0 to */SLICE_482.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_8_3
CTOF_DEL    ---     0.238 */SLICE_482.C1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_504.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_504.B0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.232 */SLICE_504.F0 to */SLICE_504.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_504.A1 to */SLICE_504.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         1   e 0.908 */SLICE_504.F1 to */SLICE_624.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5_N_2L1
CTOF_DEL    ---     0.238 */SLICE_624.C0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_49.Q1 to */SLICE_565.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_565.C0 to */SLICE_565.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_565
ROUTE         2   e 0.908 */SLICE_565.F0 to */SLICE_482.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_8_3
CTOF_DEL    ---     0.238 */SLICE_482.C1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_639.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_639.D1 to */SLICE_639.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639
ROUTE         1   e 0.908 */SLICE_639.F1 to */SLICE_484.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_RNISTO81[0]
CTOF_DEL    ---     0.238 */SLICE_484.A1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_661.CLK to */SLICE_661.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661 (from ipClk_c)
ROUTE         5   e 0.232 */SLICE_661.Q0 to */SLICE_661.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]
CTOF_DEL    ---     0.238 */SLICE_661.B0 to */SLICE_661.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661
ROUTE         1   e 0.908 */SLICE_661.F0 to */SLICE_509.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][0]
CTOF_DEL    ---     0.238 */SLICE_509.D1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_246 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_246.CLK to */SLICE_246.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_246 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_246.Q0 to */SLICE_677.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]
CTOF_DEL    ---     0.238 */SLICE_677.C0 to */SLICE_677.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_677
ROUTE         1   e 0.908 */SLICE_677.F0 to */SLICE_532.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.238 */SLICE_532.A0 to */SLICE_532.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.232 */SLICE_532.F0 to */SLICE_532.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.238 */SLICE_532.C1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_504.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_504.A0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.232 */SLICE_504.F0 to */SLICE_504.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_504.A1 to */SLICE_504.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         1   e 0.908 */SLICE_504.F1 to */SLICE_624.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5_N_2L1
CTOF_DEL    ---     0.238 */SLICE_624.C0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_48.CLK to *u/SLICE_48.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_48.Q0 to */SLICE_565.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_565.D0 to */SLICE_565.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_565
ROUTE         2   e 0.908 */SLICE_565.F0 to */SLICE_482.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_8_3
CTOF_DEL    ---     0.238 */SLICE_482.C1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_639.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_639.D1 to */SLICE_639.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639
ROUTE         1   e 0.908 */SLICE_639.F1 to */SLICE_484.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_RNISTO81[0]
CTOF_DEL    ---     0.238 */SLICE_484.A1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_482.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_482.A1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/SLICE_295 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_295.CLK to */SLICE_295.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/SLICE_295 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_295.Q0 to */SLICE_509.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]
CTOF_DEL    ---     0.238 */SLICE_509.C0 to */SLICE_509.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.232 */SLICE_509.F0 to */SLICE_509.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.238 */SLICE_509.C1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.792ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.715ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_639.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_639.D1 to */SLICE_639.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639
ROUTE         1   e 0.908 */SLICE_639.F1 to */SLICE_484.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_RNISTO81[0]
CTOF_DEL    ---     0.238 */SLICE_484.A1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.715   (26.4% logic, 73.6% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.787ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.710ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_531.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_531.A0 to */SLICE_531.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.232 */SLICE_531.F0 to */SLICE_531.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_531.C1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.710   (26.3% logic, 73.7% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.787ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_278 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.710ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_278.CLK to */SLICE_278.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_278 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_278.Q0 to */SLICE_531.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]
CTOF_DEL    ---     0.238 */SLICE_531.B0 to */SLICE_531.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.232 */SLICE_531.F0 to */SLICE_531.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_531.C1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.710   (26.3% logic, 73.7% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.787ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_283 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.710ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_283.CLK to */SLICE_283.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_283 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_283.Q0 to */SLICE_531.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]
CTOF_DEL    ---     0.238 */SLICE_531.C0 to */SLICE_531.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.232 */SLICE_531.F0 to */SLICE_531.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_531.C1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.710   (26.3% logic, 73.7% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.483ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_252 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.406ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_252.CLK to */SLICE_252.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_252 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_252.Q0 to */SLICE_455.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]
CTOOFX_DEL  ---     0.399 */SLICE_455.A0 to *LICE_455.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/rd_dout_te_1_u[0]/SLICE_455
ROUTE         1   e 0.908 *LICE_455.OFX0 to */SLICE_624.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.238 */SLICE_624.A0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.406   (26.4% logic, 73.6% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.483ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_253 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.406ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_253.CLK to */SLICE_253.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_253 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_253.Q0 to */SLICE_455.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]
CTOOFX_DEL  ---     0.399 */SLICE_455.D0 to *LICE_455.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/rd_dout_te_1_u[0]/SLICE_455
ROUTE         1   e 0.908 *LICE_455.OFX0 to */SLICE_624.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.238 */SLICE_624.A0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.406   (26.4% logic, 73.6% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.483ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_255 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.406ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_255.CLK to */SLICE_255.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_255 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_255.Q0 to */SLICE_455.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]
CTOOFX_DEL  ---     0.399 */SLICE_455.D1 to *LICE_455.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/rd_dout_te_1_u[0]/SLICE_455
ROUTE         1   e 0.908 *LICE_455.OFX0 to */SLICE_624.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.238 */SLICE_624.A0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.406   (26.4% logic, 73.6% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_615.Q0 to */SLICE_721.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_721.B0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_721.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_721.A0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_721.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_721.D0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_615.Q0 to */SLICE_721.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_721.B0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_721.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_721.D0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_642.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_642.A0 to */SLICE_642.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         4   e 0.908 */SLICE_642.F0 to */SLICE_510.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_1
CTOF_DEL    ---     0.238 */SLICE_510.B1 to */SLICE_510.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_510
ROUTE         1   e 0.908 */SLICE_510.F1 to */SLICE_533.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/un6_rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_533.D1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to */SLICE_642.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_642.A1 to */SLICE_642.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         1   e 0.908 */SLICE_642.F1 to */SLICE_510.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][1]
CTOF_DEL    ---     0.238 */SLICE_510.D1 to */SLICE_510.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_510
ROUTE         1   e 0.908 */SLICE_510.F1 to */SLICE_533.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/un6_rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_533.D1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_642.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_642.A0 to */SLICE_642.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         4   e 0.908 */SLICE_642.F0 to */SLICE_509.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_1
CTOF_DEL    ---     0.238 */SLICE_509.B1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_642.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_642.B0 to */SLICE_642.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         4   e 0.908 */SLICE_642.F0 to */SLICE_509.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_1
CTOF_DEL    ---     0.238 */SLICE_509.B1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_642.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_642.B0 to */SLICE_642.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         4   e 0.908 */SLICE_642.F0 to */SLICE_510.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_1
CTOF_DEL    ---     0.238 */SLICE_510.B1 to */SLICE_510.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_510
ROUTE         1   e 0.908 */SLICE_510.F1 to */SLICE_533.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/un6_rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_533.D1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_531.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_531.A1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_534.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_534.A0 to */SLICE_534.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_534
ROUTE         4   e 0.908 */SLICE_534.F0 to */SLICE_509.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_0
CTOF_DEL    ---     0.238 */SLICE_509.A1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to */SLICE_661.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_661.A0 to */SLICE_661.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661
ROUTE         1   e 0.908 */SLICE_661.F0 to */SLICE_509.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][0]
CTOF_DEL    ---     0.238 */SLICE_509.D1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_534.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_534.B0 to */SLICE_534.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_534
ROUTE         4   e 0.908 */SLICE_534.F0 to */SLICE_509.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_0
CTOF_DEL    ---     0.238 */SLICE_509.A1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         5   e 0.908 */SLICE_103.Q0 to */SLICE_628.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.238 */SLICE_628.A0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_103.Q1 to */SLICE_628.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]
CTOF_DEL    ---     0.238 */SLICE_628.B0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_721.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_721.C0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_534.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_534.B0 to */SLICE_534.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_534
ROUTE         4   e 0.908 */SLICE_534.F0 to */SLICE_510.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_0
CTOF_DEL    ---     0.238 */SLICE_510.A1 to */SLICE_510.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_510
ROUTE         1   e 0.908 */SLICE_510.F1 to */SLICE_533.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/un6_rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_533.D1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_531.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_531.B1 to */SLICE_531.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_531
ROUTE         1   e 0.908 */SLICE_531.F1 to */SLICE_530.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te_1_1_0[0]
CTOF_DEL    ---     0.238 */SLICE_530.D1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_103.Q1 to */SLICE_628.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]
CTOF_DEL    ---     0.238 */SLICE_628.B0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_301 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_301.CLK to */SLICE_301.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_301 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_301.Q0 to */SLICE_661.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]
CTOF_DEL    ---     0.238 */SLICE_661.C0 to */SLICE_661.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661
ROUTE         1   e 0.908 */SLICE_661.F0 to */SLICE_509.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][0]
CTOF_DEL    ---     0.238 */SLICE_509.D1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_721.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_721.C0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_721.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_721.A0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_534.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_534.A0 to */SLICE_534.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_534
ROUTE         4   e 0.908 */SLICE_534.F0 to */SLICE_510.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_0
CTOF_DEL    ---     0.238 */SLICE_510.A1 to */SLICE_510.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_510
ROUTE         1   e 0.908 */SLICE_510.F1 to */SLICE_533.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/un6_rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_533.D1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_301 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_301.CLK to */SLICE_301.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_301 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_301.Q1 to */SLICE_642.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]
CTOF_DEL    ---     0.238 */SLICE_642.B1 to */SLICE_642.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         1   e 0.908 */SLICE_642.F1 to */SLICE_510.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][1]
CTOF_DEL    ---     0.238 */SLICE_510.D1 to */SLICE_510.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_510
ROUTE         1   e 0.908 */SLICE_510.F1 to */SLICE_533.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/un6_rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_533.D1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.317ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (7.240ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         5   e 0.908 */SLICE_103.Q0 to */SLICE_628.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.238 */SLICE_628.A0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    7.240   (24.7% logic, 75.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.227ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (7.001ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_503.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_503.B1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    7.001   (22.2% logic, 77.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.227ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (7.001ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_504.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_504.B0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    7.001   (22.2% logic, 77.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.227ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (7.001ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_504.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_504.A0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    7.001   (22.2% logic, 77.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.227ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (7.001ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_503.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_503.A1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    7.001   (22.2% logic, 77.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.116ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.039ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_611.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_611.A1 to */SLICE_611.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_611
ROUTE         1   e 0.908 */SLICE_611.F1 to */SLICE_572.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_RNI9SJP
CTOF_DEL    ---     0.238 */SLICE_572.A1 to */SLICE_572.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572
ROUTE         1   e 0.232 */SLICE_572.F1 to */SLICE_572.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_RNI90OG1
CTOF_DEL    ---     0.238 */SLICE_572.B0 to */SLICE_572.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572
ROUTE         2   e 0.908 */SLICE_572.F0 to */SLICE_484.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNI2KBD3
CTOF_DEL    ---     0.238 */SLICE_484.C1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.039   (28.9% logic, 71.1% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.116ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_677 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.039ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_677.CLK to */SLICE_677.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_677 (from ipClk_c)
ROUTE         2   e 0.232 */SLICE_677.Q0 to */SLICE_677.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]
CTOF_DEL    ---     0.238 */SLICE_677.B0 to */SLICE_677.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_677
ROUTE         1   e 0.908 */SLICE_677.F0 to */SLICE_532.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.238 */SLICE_532.A0 to */SLICE_532.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.232 */SLICE_532.F0 to */SLICE_532.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.238 */SLICE_532.C1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.039   (28.9% logic, 71.1% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.116ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.039ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_307.CLK to */SLICE_307.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (from jtaghub16_jtck)
ROUTE        28   e 0.908 */SLICE_307.Q0 to */SLICE_482.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[0]
CTOF_DEL    ---     0.238 */SLICE_482.D0 to */SLICE_482.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.232 */SLICE_482.F0 to */SLICE_482.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_0_o5_1_1
CTOF_DEL    ---     0.238 */SLICE_482.B1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.039   (28.9% logic, 71.1% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    7.116ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.039ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_509.CLK to */SLICE_509.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509 (from ipClk_c)
ROUTE         5   e 0.232 */SLICE_509.Q0 to */SLICE_509.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]
CTOF_DEL    ---     0.238 */SLICE_509.B0 to */SLICE_509.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.232 */SLICE_509.F0 to */SLICE_509.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.238 */SLICE_509.C1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.039   (28.9% logic, 71.1% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    7.116ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (7.039ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_482.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_482.A0 to */SLICE_482.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.232 */SLICE_482.F0 to */SLICE_482.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_0_o5_1_1
CTOF_DEL    ---     0.238 */SLICE_482.B1 to */SLICE_482.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_482
ROUTE         1   e 0.908 */SLICE_482.F1 to */SLICE_567.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_7_0
CTOF_DEL    ---     0.238 */SLICE_567.A0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    7.039   (28.9% logic, 71.1% route), 8 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.646ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (6.569ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_530.CLK to */SLICE_530.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530 (from ipClk_c)
ROUTE         4   e 0.232 */SLICE_530.Q0 to */SLICE_530.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]
CTOF_DEL    ---     0.238 */SLICE_530.B1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    6.569   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.646ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_164 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (6.569ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_164.CLK to */SLICE_164.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_164 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_164.Q0 to */SLICE_564.A0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[0]
CTOF_DEL    ---     0.238 */SLICE_564.A0 to */SLICE_564.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_564
ROUTE         3   e 0.908 */SLICE_564.F0 to */SLICE_639.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_m6_i_a3_N_2_1_0
CTOF_DEL    ---     0.238 */SLICE_639.B1 to */SLICE_639.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639
ROUTE         1   e 0.908 */SLICE_639.F1 to */SLICE_484.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_RNISTO81[0]
CTOF_DEL    ---     0.238 */SLICE_484.A1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    6.569   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.646ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (6.569ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_153.CLK to */SLICE_153.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_153.Q0 to */SLICE_564.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]
CTOF_DEL    ---     0.238 */SLICE_564.D0 to */SLICE_564.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_564
ROUTE         3   e 0.908 */SLICE_564.F0 to */SLICE_639.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_m6_i_a3_N_2_1_0
CTOF_DEL    ---     0.238 */SLICE_639.B1 to */SLICE_639.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639
ROUTE         1   e 0.908 */SLICE_639.F1 to */SLICE_484.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_RNISTO81[0]
CTOF_DEL    ---     0.238 */SLICE_484.A1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    6.569   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.646ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_248 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (6.569ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_248.CLK to */SLICE_248.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_248 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_248.Q0 to */SLICE_532.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]
CTOF_DEL    ---     0.238 */SLICE_532.C0 to */SLICE_532.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.232 */SLICE_532.F0 to */SLICE_532.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.238 */SLICE_532.C1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_484.D0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_484.D0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    6.569   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/SLICE_295 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_295.CLK to */SLICE_295.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/SLICE_295 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_295.Q0 to */SLICE_509.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]
CTOF_DEL    ---     0.238 */SLICE_509.C0 to */SLICE_509.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.232 */SLICE_509.F0 to */SLICE_509.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.238 */SLICE_509.C1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_615.Q0 to */SLICE_721.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_721.B0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_661.CLK to */SLICE_661.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661 (from ipClk_c)
ROUTE         5   e 0.232 */SLICE_661.Q0 to */SLICE_661.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]
CTOF_DEL    ---     0.238 */SLICE_661.B0 to */SLICE_661.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_661
ROUTE         1   e 0.908 */SLICE_661.F0 to */SLICE_509.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][0]
CTOF_DEL    ---     0.238 */SLICE_509.D1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_615.Q0 to */SLICE_721.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_721.B0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_504.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_504.B0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.232 */SLICE_504.F0 to */SLICE_504.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_504.A1 to */SLICE_504.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         1   e 0.908 */SLICE_504.F1 to */SLICE_624.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5_N_2L1
CTOF_DEL    ---     0.238 */SLICE_624.C0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_721.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_721.C0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_103.Q1 to */SLICE_628.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]
CTOF_DEL    ---     0.238 */SLICE_628.B0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_721.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_721.A0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_246 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_246.CLK to */SLICE_246.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_246 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_246.Q0 to */SLICE_677.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]
CTOF_DEL    ---     0.238 */SLICE_677.C0 to */SLICE_677.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_677
ROUTE         1   e 0.908 */SLICE_677.F0 to */SLICE_532.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.238 */SLICE_532.A0 to */SLICE_532.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.232 */SLICE_532.F0 to */SLICE_532.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.238 */SLICE_532.C1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_721.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_721.C0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_721.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_721.D0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_721.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_721.A0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_721.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_721.D0 to */SLICE_721.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_721
ROUTE         1   e 0.908 */SLICE_721.F0 to */SLICE_503.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_503.C1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         5   e 0.908 */SLICE_103.Q0 to */SLICE_628.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.238 */SLICE_628.A0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_504.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_504.A0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.232 */SLICE_504.F0 to */SLICE_504.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_504.A1 to */SLICE_504.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         1   e 0.908 */SLICE_504.F1 to */SLICE_624.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5_N_2L1
CTOF_DEL    ---     0.238 */SLICE_624.C0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_103.Q1 to */SLICE_628.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]
CTOF_DEL    ---     0.238 */SLICE_628.B0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         5   e 0.908 */SLICE_103.Q0 to */SLICE_628.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.238 */SLICE_628.A0 to */SLICE_628.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628
ROUTE         1   e 0.908 */SLICE_628.F0 to */SLICE_503.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_1
CTOF_DEL    ---     0.238 */SLICE_503.D1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.641ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/SLICE_295 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (6.564ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_295.CLK to */SLICE_295.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/SLICE_295 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_295.Q1 to */SLICE_510.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]
CTOF_DEL    ---     0.238 */SLICE_510.B0 to */SLICE_510.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_510
ROUTE         1   e 0.232 */SLICE_510.F0 to */SLICE_510.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[0][1]
CTOF_DEL    ---     0.238 */SLICE_510.C1 to */SLICE_510.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_510
ROUTE         1   e 0.908 */SLICE_510.F1 to */SLICE_533.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/un6_rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_533.D1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    6.564   (27.3% logic, 72.7% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.551ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (6.325ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_507.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_507.A1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    6.325   (24.6% logic, 75.4% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.551ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (6.325ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_507.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_507.B1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    6.325   (24.6% logic, 75.4% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.332ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_253 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.255ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_253.CLK to */SLICE_253.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_253 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_253.Q0 to */SLICE_455.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]
CTOOFX_DEL  ---     0.399 */SLICE_455.D0 to *LICE_455.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/rd_dout_te_1_u[0]/SLICE_455
ROUTE         1   e 0.908 *LICE_455.OFX0 to */SLICE_624.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.238 */SLICE_624.A0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.255   (27.4% logic, 72.6% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.332ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_252 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.255ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_252.CLK to */SLICE_252.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_252 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_252.Q0 to */SLICE_455.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]
CTOOFX_DEL  ---     0.399 */SLICE_455.A0 to *LICE_455.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/rd_dout_te_1_u[0]/SLICE_455
ROUTE         1   e 0.908 *LICE_455.OFX0 to */SLICE_624.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.238 */SLICE_624.A0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.255   (27.4% logic, 72.6% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    6.332ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_255 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.255ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_255.CLK to */SLICE_255.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_255 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_255.Q0 to */SLICE_455.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]
CTOOFX_DEL  ---     0.399 */SLICE_455.D1 to *LICE_455.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/rd_dout_te_1_u[0]/SLICE_455
ROUTE         1   e 0.908 *LICE_455.OFX0 to */SLICE_624.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[0][0]
CTOF_DEL    ---     0.238 */SLICE_624.A0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.255   (27.4% logic, 72.6% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_49.Q1 to */SLICE_629.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_629.C0 to */SLICE_629.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F0 to */SLICE_557.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.238 */SLICE_557.D0 to */SLICE_557.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.908 */SLICE_557.F0 to */SLICE_537.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_69
CTOF_DEL    ---     0.238 */SLICE_537.A0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_504.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_504.B0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_504.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_504.A0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_504.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_504.B0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_503.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_503.B1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_558.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_558.A0 to */SLICE_558.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         1   e 0.908 */SLICE_558.F0 to */SLICE_537.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1030
CTOF_DEL    ---     0.238 */SLICE_537.B0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_642.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_642.A0 to */SLICE_642.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         4   e 0.908 */SLICE_642.F0 to */SLICE_511.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_1
CTOF_DEL    ---     0.238 */SLICE_511.B1 to */SLICE_511.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511
ROUTE         1   e 0.908 */SLICE_511.F1 to */SLICE_505.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_2L1
CTOF_DEL    ---     0.238 */SLICE_505.B1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to */SLICE_662.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_662.A0 to */SLICE_662.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_662
ROUTE         1   e 0.908 */SLICE_662.F0 to */SLICE_511.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][2]
CTOF_DEL    ---     0.238 */SLICE_511.D1 to */SLICE_511.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511
ROUTE         1   e 0.908 */SLICE_511.F1 to */SLICE_505.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_2L1
CTOF_DEL    ---     0.238 */SLICE_505.B1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_51.CLK to *u/SLICE_51.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (from jtaghub16_jtck)
ROUTE         4   e 0.908 *u/SLICE_51.Q1 to */SLICE_629.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_629.A0 to */SLICE_629.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F0 to */SLICE_557.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.238 */SLICE_557.D0 to */SLICE_557.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.908 */SLICE_557.F0 to */SLICE_537.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_69
CTOF_DEL    ---     0.238 */SLICE_537.A0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_504.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_504.A0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_534.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_534.A0 to */SLICE_534.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_534
ROUTE         4   e 0.908 */SLICE_534.F0 to */SLICE_511.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_0
CTOF_DEL    ---     0.238 */SLICE_511.A1 to */SLICE_511.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511
ROUTE         1   e 0.908 */SLICE_511.F1 to */SLICE_505.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_2L1
CTOF_DEL    ---     0.238 */SLICE_505.B1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_642.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_642.B0 to */SLICE_642.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_642
ROUTE         4   e 0.908 */SLICE_642.F0 to */SLICE_511.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_1
CTOF_DEL    ---     0.238 */SLICE_511.B1 to */SLICE_511.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511
ROUTE         1   e 0.908 */SLICE_511.F1 to */SLICE_505.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_2L1
CTOF_DEL    ---     0.238 */SLICE_505.B1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_48.CLK to *u/SLICE_48.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_48.Q0 to */SLICE_629.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_629.D0 to */SLICE_629.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F0 to */SLICE_557.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.238 */SLICE_557.D0 to */SLICE_557.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.908 */SLICE_557.F0 to */SLICE_537.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_69
CTOF_DEL    ---     0.238 */SLICE_537.A0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         4   e 0.908 *u/SLICE_50.Q0 to */SLICE_629.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_629.B0 to */SLICE_629.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F0 to */SLICE_557.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un19_jtdo_3
CTOF_DEL    ---     0.238 */SLICE_557.D0 to */SLICE_557.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.908 */SLICE_557.F0 to */SLICE_537.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_69
CTOF_DEL    ---     0.238 */SLICE_537.A0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_504.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_504.A0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_503.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_503.A1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_504.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_504.A0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_503.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_503.A1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_534.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_534.B0 to */SLICE_534.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_534
ROUTE         4   e 0.908 */SLICE_534.F0 to */SLICE_511.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/_decfrac0_0
CTOF_DEL    ---     0.238 */SLICE_511.A1 to */SLICE_511.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511
ROUTE         1   e 0.908 */SLICE_511.F1 to */SLICE_505.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_2L1
CTOF_DEL    ---     0.238 */SLICE_505.B1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_504.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_504.B0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_503.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_503.B1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (6.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_504.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_504.B0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_507.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_507.C0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    6.094   (25.5% logic, 74.5% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_477.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_477.A1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_507.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_507.B0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_477.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_477.B1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_507.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_507.A0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_600.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_600.A1 to */SLICE_600.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_600
ROUTE         1   e 0.908 */SLICE_600.F1 to */SLICE_506.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_N_2L1
CTOF_DEL    ---     0.238 */SLICE_506.C0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_477.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_477.C1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    6.081ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.855ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.855   (22.5% logic, 77.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.970ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (5.893ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_572.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_572.D1 to */SLICE_572.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572
ROUTE         1   e 0.232 */SLICE_572.F1 to */SLICE_572.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_RNI90OG1
CTOF_DEL    ---     0.238 */SLICE_572.B0 to */SLICE_572.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572
ROUTE         2   e 0.908 */SLICE_572.F0 to */SLICE_484.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNI2KBD3
CTOF_DEL    ---     0.238 */SLICE_484.C1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.893   (30.5% logic, 69.5% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.970ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (5.893ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_572.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_572.C1 to */SLICE_572.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572
ROUTE         1   e 0.232 */SLICE_572.F1 to */SLICE_572.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_RNI90OG1
CTOF_DEL    ---     0.238 */SLICE_572.B0 to */SLICE_572.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572
ROUTE         2   e 0.908 */SLICE_572.F0 to */SLICE_484.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNI2KBD3
CTOF_DEL    ---     0.238 */SLICE_484.C1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.893   (30.5% logic, 69.5% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.970ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (5.893ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_221.CLK to */SLICE_221.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_221.Q0 to */SLICE_567.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[0]
CTOF_DEL    ---     0.238 */SLICE_567.C1 to */SLICE_567.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.232 */SLICE_567.F1 to */SLICE_567.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_3
CTOF_DEL    ---     0.238 */SLICE_567.C0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.893   (30.5% logic, 69.5% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.970ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (5.893ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_118.CLK to */SLICE_118.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_118.Q0 to */SLICE_567.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]
CTOF_DEL    ---     0.238 */SLICE_567.B1 to */SLICE_567.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.232 */SLICE_567.F1 to */SLICE_567.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_3
CTOF_DEL    ---     0.238 */SLICE_567.C0 to */SLICE_567.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_567
ROUTE         1   e 0.908 */SLICE_567.F0 to */SLICE_484.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_2
CTOF_DEL    ---     0.238 */SLICE_484.D1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.893   (30.5% logic, 69.5% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.965ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.888ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_509.CLK to */SLICE_509.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509 (from ipClk_c)
ROUTE         5   e 0.232 */SLICE_509.Q0 to */SLICE_509.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]
CTOF_DEL    ---     0.238 */SLICE_509.B0 to */SLICE_509.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.232 */SLICE_509.F0 to */SLICE_509.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[0][0]
CTOF_DEL    ---     0.238 */SLICE_509.C1 to */SLICE_509.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_509
ROUTE         1   e 0.908 */SLICE_509.F1 to */SLICE_532.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_1_N_2L1
CTOF_DEL    ---     0.238 */SLICE_532.D1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.888   (30.4% logic, 69.6% route), 7 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.965ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_677 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.888ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_677.CLK to */SLICE_677.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_677 (from ipClk_c)
ROUTE         2   e 0.232 */SLICE_677.Q0 to */SLICE_677.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]
CTOF_DEL    ---     0.238 */SLICE_677.B0 to */SLICE_677.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_677
ROUTE         1   e 0.908 */SLICE_677.F0 to */SLICE_532.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/N_31
CTOF_DEL    ---     0.238 */SLICE_532.A0 to */SLICE_532.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.232 */SLICE_532.F0 to */SLICE_532.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.238 */SLICE_532.C1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.888   (30.4% logic, 69.6% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.500ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (5.423ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_569.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_569.C0 to */SLICE_569.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_569
ROUTE         1   e 0.232 */SLICE_569.F0 to */SLICE_569.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_11_2
CTOF_DEL    ---     0.238 */SLICE_569.B1 to */SLICE_569.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_569
ROUTE         1   e 0.908 */SLICE_569.F1 to */SLICE_484.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_RNI04UC1
CTOF_DEL    ---     0.238 */SLICE_484.A0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.423   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.500ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (5.423ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_141.CLK to */SLICE_141.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_141.Q0 to */SLICE_639.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]
CTOF_DEL    ---     0.238 */SLICE_639.C1 to */SLICE_639.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639
ROUTE         1   e 0.908 */SLICE_639.F1 to */SLICE_484.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_RNISTO81[0]
CTOF_DEL    ---     0.238 */SLICE_484.A1 to */SLICE_484.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         1   e 0.232 */SLICE_484.F1 to */SLICE_484.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w_RNIRU60A
CTOF_DEL    ---     0.238 */SLICE_484.C0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    5.423   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.232 */SLICE_558.F1 to */SLICE_558.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_558.B0 to */SLICE_558.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         1   e 0.908 */SLICE_558.F0 to */SLICE_537.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1030
CTOF_DEL    ---     0.238 */SLICE_537.B0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_530.CLK to */SLICE_530.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530 (from ipClk_c)
ROUTE         4   e 0.232 */SLICE_530.Q0 to */SLICE_530.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]
CTOF_DEL    ---     0.238 */SLICE_530.B1 to */SLICE_530.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         1   e 0.908 */SLICE_530.F1 to */SLICE_624.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][0]
CTOF_DEL    ---     0.238 */SLICE_624.B0 to */SLICE_624.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_624
ROUTE         1   e 0.908 */SLICE_624.F0 to */SLICE_535.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_4L5
CTOF_DEL    ---     0.238 */SLICE_535.C0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_562.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_562.A0 to */SLICE_562.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_562
ROUTE         1   e 0.232 */SLICE_562.F0 to */SLICE_562.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_m4_e_2_N_2L1
CTOF_DEL    ---     0.238 */SLICE_562.C1 to */SLICE_562.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_562
ROUTE         1   e 0.908 */SLICE_562.F1 to */SLICE_563.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_3_2_1
CTOF_DEL    ---     0.238 */SLICE_563.C1 to */SLICE_563.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_563
ROUTE         2   e 0.908 */SLICE_563.F1 to */SLICE_566.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_m4_e_2
CTOF_DEL    ---     0.238 */SLICE_566.C1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_530.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_530.B0 to */SLICE_530.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         2   e 0.908 */SLICE_530.F0 to */SLICE_528.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te35
CTOF_DEL    ---     0.238 */SLICE_528.B0 to */SLICE_528.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.232 */SLICE_528.F0 to */SLICE_528.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][1]
CTOF_DEL    ---     0.238 */SLICE_528.B1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_562.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_562.B0 to */SLICE_562.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_562
ROUTE         1   e 0.232 */SLICE_562.F0 to */SLICE_562.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_m4_e_2_N_2L1
CTOF_DEL    ---     0.238 */SLICE_562.C1 to */SLICE_562.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_562
ROUTE         1   e 0.908 */SLICE_562.F1 to */SLICE_563.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_3_2_1
CTOF_DEL    ---     0.238 */SLICE_563.C1 to */SLICE_563.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_563
ROUTE         2   e 0.908 */SLICE_563.F1 to */SLICE_566.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_m4_e_2
CTOF_DEL    ---     0.238 */SLICE_566.C1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_559.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_559.A0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_49.Q0 to */SLICE_557.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_557.B1 to */SLICE_557.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.232 */SLICE_557.F1 to */SLICE_557.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un19_jtdo_2
CTOF_DEL    ---     0.238 */SLICE_557.C0 to */SLICE_557.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.908 */SLICE_557.F0 to */SLICE_537.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_69
CTOF_DEL    ---     0.238 */SLICE_537.A0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_503.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_503.B1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_507.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_507.A1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_507.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_507.B1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_481.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_481.C1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_503.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_503.B1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_561.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_561.B1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_559.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_559.A0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_662 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_662.CLK to */SLICE_662.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_662 (from ipClk_c)
ROUTE         5   e 0.232 */SLICE_662.Q0 to */SLICE_662.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]
CTOF_DEL    ---     0.238 */SLICE_662.B0 to */SLICE_662.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/SLICE_662
ROUTE         1   e 0.908 */SLICE_662.F0 to */SLICE_511.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[1][2]
CTOF_DEL    ---     0.238 */SLICE_511.D1 to */SLICE_511.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511
ROUTE         1   e 0.908 */SLICE_511.F1 to */SLICE_505.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_2L1
CTOF_DEL    ---     0.238 */SLICE_505.B1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.232 */SLICE_558.F1 to */SLICE_558.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_558.B0 to */SLICE_558.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         1   e 0.908 */SLICE_558.F0 to */SLICE_537.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1030
CTOF_DEL    ---     0.238 */SLICE_537.B0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_507.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_507.B1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_481.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_481.C1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_507.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_507.B1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_507.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_507.A1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_481.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_481.C1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_478.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_478.C1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_507.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_507.A1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_478.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_478.C1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_566.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_566.D0 to */SLICE_566.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         2   e 0.232 */SLICE_566.F0 to */SLICE_566.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_N_6_0
CTOF_DEL    ---     0.238 */SLICE_566.A1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_566.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_566.D0 to */SLICE_566.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         2   e 0.232 */SLICE_566.F0 to */SLICE_566.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_N_6_0
CTOF_DEL    ---     0.238 */SLICE_566.A1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_530.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_530.A0 to */SLICE_530.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_530
ROUTE         2   e 0.908 */SLICE_530.F0 to */SLICE_528.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/rd_dout_te35
CTOF_DEL    ---     0.238 */SLICE_528.B0 to */SLICE_528.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.232 */SLICE_528.F0 to */SLICE_528.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][1]
CTOF_DEL    ---     0.238 */SLICE_528.B1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_503.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_503.A1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_478.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_478.C1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_503.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_503.A1 to */SLICE_503.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_503
ROUTE         7   e 0.908 */SLICE_503.F1 to */SLICE_477.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen
CTOF_DEL    ---     0.238 */SLICE_477.D1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_50.Q1 to */SLICE_557.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_557.A1 to */SLICE_557.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.232 */SLICE_557.F1 to */SLICE_557.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un19_jtdo_2
CTOF_DEL    ---     0.238 */SLICE_557.C0 to */SLICE_557.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.908 */SLICE_557.F0 to */SLICE_537.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_69
CTOF_DEL    ---     0.238 */SLICE_537.A0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_481.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_481.C1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_246 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_246.CLK to */SLICE_246.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_246 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_246.Q1 to */SLICE_533.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]
CTOF_DEL    ---     0.238 */SLICE_533.C0 to */SLICE_533.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.232 */SLICE_533.F0 to */SLICE_533.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[1]
CTOF_DEL    ---     0.238 */SLICE_533.C1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_478.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_478.C1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_248 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_248.CLK to */SLICE_248.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_248 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_248.Q0 to */SLICE_532.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]
CTOF_DEL    ---     0.238 */SLICE_532.C0 to */SLICE_532.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.232 */SLICE_532.F0 to */SLICE_532.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[0]
CTOF_DEL    ---     0.238 */SLICE_532.C1 to */SLICE_532.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_532
ROUTE         1   e 0.908 */SLICE_532.F1 to */SLICE_535.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/N_90
CTOF_DEL    ---     0.238 */SLICE_535.A0 to */SLICE_535.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         5   e 0.908 */SLICE_535.F0 to */SLICE_566.D1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[0]
CTOF_DEL    ---     0.238 */SLICE_566.D1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_507.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_507.B1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_566.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_566.D0 to */SLICE_566.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         2   e 0.232 */SLICE_566.F0 to */SLICE_566.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_N_6_0
CTOF_DEL    ---     0.238 */SLICE_566.A1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_248 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_248.CLK to */SLICE_248.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_248 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_248.Q1 to */SLICE_533.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]
CTOF_DEL    ---     0.238 */SLICE_533.D0 to */SLICE_533.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.232 */SLICE_533.F0 to */SLICE_533.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[1]
CTOF_DEL    ---     0.238 */SLICE_533.C1 to */SLICE_533.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_533
ROUTE         1   e 0.908 */SLICE_533.F1 to */SLICE_528.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_am[1]
CTOF_DEL    ---     0.238 */SLICE_528.A1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.495ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (5.418ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_507.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_507.A1 to */SLICE_507.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         1   e 0.232 */SLICE_507.F1 to */SLICE_507.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3_N_2L1
CTOF_DEL    ---     0.238 */SLICE_507.D0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    5.418   (28.7% logic, 71.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_141.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_147.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_142.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_145.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_146.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_148.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_144.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_558.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_558.B1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_143.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_141.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_142.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_144.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_142.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_145.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_144.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_145.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_146.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_148.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_615.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_615.A1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q0 to */SLICE_521.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_521.C0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q1 to */SLICE_521.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_521.D0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_148.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_147.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_521.B0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_521.B0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_148.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_147.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_146.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_143.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_142.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_141.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_615.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_615.B1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_615.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_615.B1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_145.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_141.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_615.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_615.D1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_615.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_615.A1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_615.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_615.D1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_615.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_615.A1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_615.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_615.D1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_615.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_615.A1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_143.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_142.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_615.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_615.B1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_144.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_558.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_558.A1 to */SLICE_558.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         4   e 0.908 */SLICE_558.F1 to */SLICE_466.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1054
CTOF_DEL    ---     0.238 */SLICE_466.B1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_145.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_146.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_141.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_143.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_143.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_144.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_147.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_615.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_615.B1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_146.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_147.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_466.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_466.A1 to */SLICE_466.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.232 */SLICE_466.F1 to */SLICE_466.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1049
CTOF_DEL    ---     0.238 */SLICE_466.B0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_148.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.405ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (5.179ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_615.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_615.D1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    5.179   (25.4% logic, 74.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.030ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (4.953ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_104.CLK to */SLICE_104.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_104.Q0 to */SLICE_569.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc
CTOF_DEL    ---     0.238 */SLICE_569.D1 to */SLICE_569.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_569
ROUTE         1   e 0.908 */SLICE_569.F1 to */SLICE_484.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_RNI04UC1
CTOF_DEL    ---     0.238 */SLICE_484.A0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    4.953   (26.7% logic, 73.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.030ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (4.953ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_569.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_569.C1 to */SLICE_569.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_569
ROUTE         1   e 0.908 */SLICE_569.F1 to */SLICE_484.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_RNI04UC1
CTOF_DEL    ---     0.238 */SLICE_484.A0 to */SLICE_484.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_484
ROUTE         2   e 0.908 */SLICE_484.F0 to */SLICE_627.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1_1_0
CTOF_DEL    ---     0.238 */SLICE_627.B0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    4.953   (26.7% logic, 73.3% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_550.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_550.D0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_726 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_726.CLK to */SLICE_726.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_726 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_726.Q0 to */SLICE_675.C0 Test_reveal_coretop_instance/test_la0_inst_0/even_parity
CTOF_DEL    ---     0.238 */SLICE_675.C0 to */SLICE_675.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_675
ROUTE         1   e 0.908 */SLICE_675.F0 to */SLICE_505.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[2]
CTOF_DEL    ---     0.238 */SLICE_505.C1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_704.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_704.B0 to */SLICE_704.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_704
ROUTE         1   e 0.908 */SLICE_704.F0 to */SLICE_131.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_720
CTOF_DEL    ---     0.238 */SLICE_131.A0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_702.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_702.B0 to */SLICE_702.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_702
ROUTE         1   e 0.908 */SLICE_702.F0 to */SLICE_130.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_688
CTOF_DEL    ---     0.238 */SLICE_130.A0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_700.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_700.B0 to */SLICE_700.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_700
ROUTE         1   e 0.908 */SLICE_700.F0 to */SLICE_129.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_656
CTOF_DEL    ---     0.238 */SLICE_129.A0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_698.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_698.B0 to */SLICE_698.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_698
ROUTE         1   e 0.908 */SLICE_698.F0 to */SLICE_128.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_624
CTOF_DEL    ---     0.238 */SLICE_128.A0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_696.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_696.B0 to */SLICE_696.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_696
ROUTE         1   e 0.908 */SLICE_696.F0 to */SLICE_127.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_592
CTOF_DEL    ---     0.238 */SLICE_127.A0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_694.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_694.B0 to */SLICE_694.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_694
ROUTE         1   e 0.908 */SLICE_694.F0 to */SLICE_126.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_560
CTOF_DEL    ---     0.238 */SLICE_126.A0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_616.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_616.B1 to */SLICE_616.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F1 to */SLICE_125.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_82
CTOF_DEL    ---     0.238 */SLICE_125.A0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_553.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_553.D0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_553.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_553.D0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_552.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_552.D0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_552.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_552.D0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_221.CLK to */SLICE_221.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_221.Q0 to */SLICE_558.D0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[0]
CTOF_DEL    ---     0.238 */SLICE_558.D0 to */SLICE_558.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         1   e 0.908 */SLICE_558.F0 to */SLICE_537.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1030
CTOF_DEL    ---     0.238 */SLICE_537.B0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_562.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_562.D1 to */SLICE_562.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_562
ROUTE         1   e 0.908 */SLICE_562.F1 to */SLICE_563.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_3_2_1
CTOF_DEL    ---     0.238 */SLICE_563.C1 to */SLICE_563.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_563
ROUTE         2   e 0.908 */SLICE_563.F1 to */SLICE_566.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_m4_e_2
CTOF_DEL    ---     0.238 */SLICE_566.C1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_681.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_681.B0 to */SLICE_681.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_681
ROUTE         1   e 0.908 */SLICE_681.F0 to */SLICE_118.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_320
CTOF_DEL    ---     0.238 */SLICE_118.A1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_559.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_559.A0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_504.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_504.B0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_505.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_505.D1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_542.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_542.D0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_542.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_542.D0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_559.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_559.A0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_551.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_551.D0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_550.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_550.D0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_549.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_549.D0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_690.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_690.B0 to */SLICE_690.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_690
ROUTE         1   e 0.908 */SLICE_690.F0 to */SLICE_123.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_464
CTOF_DEL    ---     0.238 */SLICE_123.A0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_548.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_548.D0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_688.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_688.B0 to */SLICE_688.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_688
ROUTE         1   e 0.908 */SLICE_688.F0 to */SLICE_122.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_432
CTOF_DEL    ---     0.238 */SLICE_122.A0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_547.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_547.D0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_685.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_685.B0 to */SLICE_685.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_685
ROUTE         1   e 0.908 */SLICE_685.F0 to */SLICE_120.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_384
CTOF_DEL    ---     0.238 */SLICE_120.A1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_683.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_683.B0 to */SLICE_683.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_683
ROUTE         1   e 0.908 */SLICE_683.F0 to */SLICE_119.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_352
CTOF_DEL    ---     0.238 */SLICE_119.A1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_551.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_551.D0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_551.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_551.D0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_717.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_717.B0 to */SLICE_717.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_717
ROUTE         1   e 0.908 */SLICE_717.F0 to */SLICE_123.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_84
CTOF_DEL    ---     0.238 */SLICE_123.A1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_550.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_550.D0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_507.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_507.A0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_477.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_477.C1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_507.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_507.B0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_525.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_525.A1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_617.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_617.B1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_477.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_477.B1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_507.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_507.A0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_477.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_477.A1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_716.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_716.B0 to */SLICE_716.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_716
ROUTE         1   e 0.908 */SLICE_716.F0 to */SLICE_138.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_960
CTOF_DEL    ---     0.238 */SLICE_138.A1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_713.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_713.B0 to */SLICE_713.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_713
ROUTE         1   e 0.908 */SLICE_713.F0 to */SLICE_137.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_912
CTOF_DEL    ---     0.238 */SLICE_137.A0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_711.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_711.B0 to */SLICE_711.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_711
ROUTE         1   e 0.908 */SLICE_711.F0 to */SLICE_136.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_880
CTOF_DEL    ---     0.238 */SLICE_136.A0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_714.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_714.B0 to */SLICE_714.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_714
ROUTE         1   e 0.908 */SLICE_714.F0 to */SLICE_137.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_928
CTOF_DEL    ---     0.238 */SLICE_137.A1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_712.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_712.B0 to */SLICE_712.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_712
ROUTE         1   e 0.908 */SLICE_712.F0 to */SLICE_136.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_896
CTOF_DEL    ---     0.238 */SLICE_136.A1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_715.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_715.B0 to */SLICE_715.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_715
ROUTE         1   e 0.908 */SLICE_715.F0 to */SLICE_138.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_944
CTOF_DEL    ---     0.238 */SLICE_138.A0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_710.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_710.B0 to */SLICE_710.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_710
ROUTE         1   e 0.908 */SLICE_710.F0 to */SLICE_135.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_864
CTOF_DEL    ---     0.238 */SLICE_135.A1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_709.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_709.B0 to */SLICE_709.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_709
ROUTE         1   e 0.908 */SLICE_709.F0 to */SLICE_134.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_832
CTOF_DEL    ---     0.238 */SLICE_134.A1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_708.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_708.B0 to */SLICE_708.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_708
ROUTE         1   e 0.908 */SLICE_708.F0 to */SLICE_134.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_816
CTOF_DEL    ---     0.238 */SLICE_134.A0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_707.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_707.B0 to */SLICE_707.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_707
ROUTE         1   e 0.908 */SLICE_707.F0 to */SLICE_133.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_800
CTOF_DEL    ---     0.238 */SLICE_133.A1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_678.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_678.B0 to */SLICE_678.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_678
ROUTE         1   e 0.908 */SLICE_678.F0 to */SLICE_133.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_784
CTOF_DEL    ---     0.238 */SLICE_133.A0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_679.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_679.B0 to */SLICE_679.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_679
ROUTE         1   e 0.908 */SLICE_679.F0 to */SLICE_132.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_768
CTOF_DEL    ---     0.238 */SLICE_132.A1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_706.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_706.B0 to */SLICE_706.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_706
ROUTE         1   e 0.908 */SLICE_706.F0 to */SLICE_132.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_752
CTOF_DEL    ---     0.238 */SLICE_132.A0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_705.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_705.B0 to */SLICE_705.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_705
ROUTE         1   e 0.908 */SLICE_705.F0 to */SLICE_131.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_736
CTOF_DEL    ---     0.238 */SLICE_131.A1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_705.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_705.B0 to */SLICE_705.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_705
ROUTE         1   e 0.908 */SLICE_705.F0 to */SLICE_131.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_736
CTOF_DEL    ---     0.238 */SLICE_131.A1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_704.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_704.B0 to */SLICE_704.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_704
ROUTE         1   e 0.908 */SLICE_704.F0 to */SLICE_131.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_720
CTOF_DEL    ---     0.238 */SLICE_131.A0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_703.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_703.B0 to */SLICE_703.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_703
ROUTE         1   e 0.908 */SLICE_703.F0 to */SLICE_130.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_704
CTOF_DEL    ---     0.238 */SLICE_130.A1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_702.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_702.B0 to */SLICE_702.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_702
ROUTE         1   e 0.908 */SLICE_702.F0 to */SLICE_130.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_688
CTOF_DEL    ---     0.238 */SLICE_130.A0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_701.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_701.B0 to */SLICE_701.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_701
ROUTE         1   e 0.908 */SLICE_701.F0 to */SLICE_129.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_672
CTOF_DEL    ---     0.238 */SLICE_129.A1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_700.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_700.B0 to */SLICE_700.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_700
ROUTE         1   e 0.908 */SLICE_700.F0 to */SLICE_129.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_656
CTOF_DEL    ---     0.238 */SLICE_129.A0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_699.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_699.B0 to */SLICE_699.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_699
ROUTE         1   e 0.908 */SLICE_699.F0 to */SLICE_128.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_640
CTOF_DEL    ---     0.238 */SLICE_128.A1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_698.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_698.B0 to */SLICE_698.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_698
ROUTE         1   e 0.908 */SLICE_698.F0 to */SLICE_128.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_624
CTOF_DEL    ---     0.238 */SLICE_128.A0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_697.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_697.B0 to */SLICE_697.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_697
ROUTE         1   e 0.908 */SLICE_697.F0 to */SLICE_127.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_608
CTOF_DEL    ---     0.238 */SLICE_127.A1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_696.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_696.B0 to */SLICE_696.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_696
ROUTE         1   e 0.908 */SLICE_696.F0 to */SLICE_127.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_592
CTOF_DEL    ---     0.238 */SLICE_127.A0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_695.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_695.B0 to */SLICE_695.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_695
ROUTE         1   e 0.908 */SLICE_695.F0 to */SLICE_126.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_576
CTOF_DEL    ---     0.238 */SLICE_126.A1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_694.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_694.B0 to */SLICE_694.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_694
ROUTE         1   e 0.908 */SLICE_694.F0 to */SLICE_126.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_560
CTOF_DEL    ---     0.238 */SLICE_126.A0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_693.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_693.B0 to */SLICE_693.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_693
ROUTE         1   e 0.908 */SLICE_693.F0 to */SLICE_125.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_544
CTOF_DEL    ---     0.238 */SLICE_125.A1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_616.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_616.B1 to */SLICE_616.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F1 to */SLICE_125.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_82
CTOF_DEL    ---     0.238 */SLICE_125.A0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_692.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_692.B0 to */SLICE_692.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_692
ROUTE         1   e 0.908 */SLICE_692.F0 to */SLICE_124.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_512
CTOF_DEL    ---     0.238 */SLICE_124.A1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_551.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_551.D0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_691.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_691.B0 to */SLICE_691.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_691
ROUTE         1   e 0.908 */SLICE_691.F0 to */SLICE_124.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_496
CTOF_DEL    ---     0.238 */SLICE_124.A0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_717.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_717.B0 to */SLICE_717.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_717
ROUTE         1   e 0.908 */SLICE_717.F0 to */SLICE_123.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_84
CTOF_DEL    ---     0.238 */SLICE_123.A1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_608.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_608.A0 to */SLICE_608.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F0 to */SLICE_313.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.238 */SLICE_313.C0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_691.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_691.B0 to */SLICE_691.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_691
ROUTE         1   e 0.908 */SLICE_691.F0 to */SLICE_124.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_496
CTOF_DEL    ---     0.238 */SLICE_124.A0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_717.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_717.B0 to */SLICE_717.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_717
ROUTE         1   e 0.908 */SLICE_717.F0 to */SLICE_123.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_84
CTOF_DEL    ---     0.238 */SLICE_123.A1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_605.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_605.A0 to */SLICE_605.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F0 to */SLICE_312.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.238 */SLICE_312.C0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_608.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_608.A1 to */SLICE_608.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F1 to */SLICE_313.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[13]
CTOF_DEL    ---     0.238 */SLICE_313.C1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_690.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_690.B0 to */SLICE_690.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_690
ROUTE         1   e 0.908 */SLICE_690.F0 to */SLICE_123.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_464
CTOF_DEL    ---     0.238 */SLICE_123.A0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_689.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_689.B0 to */SLICE_689.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_689
ROUTE         1   e 0.908 */SLICE_689.F0 to */SLICE_122.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_448
CTOF_DEL    ---     0.238 */SLICE_122.A1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_688.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_688.B0 to */SLICE_688.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_688
ROUTE         1   e 0.908 */SLICE_688.F0 to */SLICE_122.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_432
CTOF_DEL    ---     0.238 */SLICE_122.A0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_547.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_547.D0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_606.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_606.A0 to */SLICE_606.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F0 to */SLICE_310.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.238 */SLICE_310.C1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_551.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_551.D0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_605.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_605.A1 to */SLICE_605.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F1 to */SLICE_312.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[11]
CTOF_DEL    ---     0.238 */SLICE_312.C1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_546.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_546.D0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_687.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_687.B0 to */SLICE_687.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_687
ROUTE         1   e 0.908 */SLICE_687.F0 to */SLICE_121.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_416
CTOF_DEL    ---     0.238 */SLICE_121.A1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_607.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_607.A0 to */SLICE_607.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F0 to */SLICE_310.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[6]
CTOF_DEL    ---     0.238 */SLICE_310.C0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_545.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_545.D0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_544.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_544.D0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_636.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_636.A0 to */SLICE_636.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE         1   e 0.908 */SLICE_636.F0 to */SLICE_309.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.238 */SLICE_309.C0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_543.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_543.D0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_549.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_549.D0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_690.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_690.B0 to */SLICE_690.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_690
ROUTE         1   e 0.908 */SLICE_690.F0 to */SLICE_123.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_464
CTOF_DEL    ---     0.238 */SLICE_123.A0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_689.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_689.B0 to */SLICE_689.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_689
ROUTE         1   e 0.908 */SLICE_689.F0 to */SLICE_122.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_448
CTOF_DEL    ---     0.238 */SLICE_122.A1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_548.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_548.D0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_548.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_548.D0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_688.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_688.B0 to */SLICE_688.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_688
ROUTE         1   e 0.908 */SLICE_688.F0 to */SLICE_122.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_432
CTOF_DEL    ---     0.238 */SLICE_122.A0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_606.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_606.A1 to */SLICE_606.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F1 to */SLICE_311.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.238 */SLICE_311.C0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_546.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_546.D0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_546.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_546.D0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_546.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_546.D0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_687.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_687.B0 to */SLICE_687.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_687
ROUTE         1   e 0.908 */SLICE_687.F0 to */SLICE_121.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_416
CTOF_DEL    ---     0.238 */SLICE_121.A1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_687.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_687.B0 to */SLICE_687.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_687
ROUTE         1   e 0.908 */SLICE_687.F0 to */SLICE_121.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_416
CTOF_DEL    ---     0.238 */SLICE_121.A1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_545.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_545.D0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_545.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_545.D0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_545.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_545.D0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_545.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_545.D0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_544.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_544.D0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_544.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_544.D0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_607.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_607.A1 to */SLICE_607.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F1 to */SLICE_309.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.238 */SLICE_309.C1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_544.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_544.D0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_544.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_544.D0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_543.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_543.D0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_543.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_543.D0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_543.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_543.D0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_543.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_543.D0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_686.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_686.B0 to */SLICE_686.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_686
ROUTE         1   e 0.908 */SLICE_686.F0 to */SLICE_121.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_400
CTOF_DEL    ---     0.238 */SLICE_121.A0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_686.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_686.B0 to */SLICE_686.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_686
ROUTE         1   e 0.908 */SLICE_686.F0 to */SLICE_121.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_400
CTOF_DEL    ---     0.238 */SLICE_121.A0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_685.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_685.B0 to */SLICE_685.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_685
ROUTE         1   e 0.908 */SLICE_685.F0 to */SLICE_120.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_384
CTOF_DEL    ---     0.238 */SLICE_120.A1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_684.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_684.B0 to */SLICE_684.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_684
ROUTE         1   e 0.908 */SLICE_684.F0 to */SLICE_120.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_368
CTOF_DEL    ---     0.238 */SLICE_120.A0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_683.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_683.B0 to */SLICE_683.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_683
ROUTE         1   e 0.908 */SLICE_683.F0 to */SLICE_119.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_352
CTOF_DEL    ---     0.238 */SLICE_119.A1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_550.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_550.D0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_550.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_550.D0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_549.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_549.D0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_549.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_549.D0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_549.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_549.D0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_690.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_690.B0 to */SLICE_690.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_690
ROUTE         1   e 0.908 */SLICE_690.F0 to */SLICE_123.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_464
CTOF_DEL    ---     0.238 */SLICE_123.A0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_689.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_689.B0 to */SLICE_689.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_689
ROUTE         1   e 0.908 */SLICE_689.F0 to */SLICE_122.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_448
CTOF_DEL    ---     0.238 */SLICE_122.A1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_548.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_548.D0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_548.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_548.D0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_548.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_548.D0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_548.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_548.D0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_688.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_688.B0 to */SLICE_688.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_688
ROUTE         1   e 0.908 */SLICE_688.F0 to */SLICE_122.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_432
CTOF_DEL    ---     0.238 */SLICE_122.A0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_547.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_547.D0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_547.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_547.D0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_547.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_547.D0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_547.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_547.D0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_547.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_547.D0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_542.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_542.D0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_682.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_682.B0 to */SLICE_682.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_682
ROUTE         1   e 0.908 */SLICE_682.F0 to */SLICE_119.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_336
CTOF_DEL    ---     0.238 */SLICE_119.A0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_691.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_691.B0 to */SLICE_691.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_691
ROUTE         1   e 0.908 */SLICE_691.F0 to */SLICE_124.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_496
CTOF_DEL    ---     0.238 */SLICE_124.A0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_717.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_717.B0 to */SLICE_717.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_717
ROUTE         1   e 0.908 */SLICE_717.F0 to */SLICE_123.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_84
CTOF_DEL    ---     0.238 */SLICE_123.A1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_550.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_550.D0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_550.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_550.D0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_681.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_681.B0 to */SLICE_681.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_681
ROUTE         1   e 0.908 */SLICE_681.F0 to */SLICE_118.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_320
CTOF_DEL    ---     0.238 */SLICE_118.A1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_681.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_681.B0 to */SLICE_681.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_681
ROUTE         1   e 0.908 */SLICE_681.F0 to */SLICE_118.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_320
CTOF_DEL    ---     0.238 */SLICE_118.A1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_551.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_551.D0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_535.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_535.A1 to */SLICE_535.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         2   e 0.908 */SLICE_535.F1 to */SLICE_528.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_sn_N_3
CTOF_DEL    ---     0.238 */SLICE_528.D1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_552.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_552.D0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_680.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_680.B0 to */SLICE_680.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_680
ROUTE         1   e 0.908 */SLICE_680.F0 to */SLICE_118.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_304
CTOF_DEL    ---     0.238 */SLICE_118.A0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_600.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_600.A0 to */SLICE_600.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_600
ROUTE         1   e 0.908 */SLICE_600.F0 to */SLICE_477.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_0[0]
CTOF_DEL    ---     0.238 */SLICE_477.C0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_600.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_600.A1 to */SLICE_600.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_600
ROUTE         1   e 0.908 */SLICE_600.F1 to */SLICE_506.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_N_2L1
CTOF_DEL    ---     0.238 */SLICE_506.C0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_477.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_477.A1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_525.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_525.C1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_617.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_617.B1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_600.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_600.A1 to */SLICE_600.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_600
ROUTE         1   e 0.908 */SLICE_600.F1 to */SLICE_506.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_N_2L1
CTOF_DEL    ---     0.238 */SLICE_506.C0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_477.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_477.C1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_507.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_507.B0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_506.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_506.D0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_716.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_716.B0 to */SLICE_716.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_716
ROUTE         1   e 0.908 */SLICE_716.F0 to */SLICE_138.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_960
CTOF_DEL    ---     0.238 */SLICE_138.A1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_713.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_713.B0 to */SLICE_713.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_713
ROUTE         1   e 0.908 */SLICE_713.F0 to */SLICE_137.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_912
CTOF_DEL    ---     0.238 */SLICE_137.A0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_711.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_711.B0 to */SLICE_711.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_711
ROUTE         1   e 0.908 */SLICE_711.F0 to */SLICE_136.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_880
CTOF_DEL    ---     0.238 */SLICE_136.A0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_714.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_714.B0 to */SLICE_714.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_714
ROUTE         1   e 0.908 */SLICE_714.F0 to */SLICE_137.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_928
CTOF_DEL    ---     0.238 */SLICE_137.A1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_715.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_715.B0 to */SLICE_715.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_715
ROUTE         1   e 0.908 */SLICE_715.F0 to */SLICE_138.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_944
CTOF_DEL    ---     0.238 */SLICE_138.A0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_710.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_710.B0 to */SLICE_710.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_710
ROUTE         1   e 0.908 */SLICE_710.F0 to */SLICE_135.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_864
CTOF_DEL    ---     0.238 */SLICE_135.A1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_709.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_709.B0 to */SLICE_709.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_709
ROUTE         1   e 0.908 */SLICE_709.F0 to */SLICE_134.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_832
CTOF_DEL    ---     0.238 */SLICE_134.A1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_708.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_708.B0 to */SLICE_708.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_708
ROUTE         1   e 0.908 */SLICE_708.F0 to */SLICE_134.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_816
CTOF_DEL    ---     0.238 */SLICE_134.A0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_707.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_707.B0 to */SLICE_707.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_707
ROUTE         1   e 0.908 */SLICE_707.F0 to */SLICE_133.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_800
CTOF_DEL    ---     0.238 */SLICE_133.A1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_678.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_678.B0 to */SLICE_678.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_678
ROUTE         1   e 0.908 */SLICE_678.F0 to */SLICE_133.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_784
CTOF_DEL    ---     0.238 */SLICE_133.A0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_679.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_679.B0 to */SLICE_679.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_679
ROUTE         1   e 0.908 */SLICE_679.F0 to */SLICE_132.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_768
CTOF_DEL    ---     0.238 */SLICE_132.A1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_706.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_706.B0 to */SLICE_706.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_706
ROUTE         1   e 0.908 */SLICE_706.F0 to */SLICE_132.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_752
CTOF_DEL    ---     0.238 */SLICE_132.A0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_705.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_705.B0 to */SLICE_705.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_705
ROUTE         1   e 0.908 */SLICE_705.F0 to */SLICE_131.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_736
CTOF_DEL    ---     0.238 */SLICE_131.A1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_705.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_705.B0 to */SLICE_705.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_705
ROUTE         1   e 0.908 */SLICE_705.F0 to */SLICE_131.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_736
CTOF_DEL    ---     0.238 */SLICE_131.A1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_704.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_704.B0 to */SLICE_704.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_704
ROUTE         1   e 0.908 */SLICE_704.F0 to */SLICE_131.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_720
CTOF_DEL    ---     0.238 */SLICE_131.A0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_704.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_704.B0 to */SLICE_704.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_704
ROUTE         1   e 0.908 */SLICE_704.F0 to */SLICE_131.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_720
CTOF_DEL    ---     0.238 */SLICE_131.A0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_703.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_703.B0 to */SLICE_703.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_703
ROUTE         1   e 0.908 */SLICE_703.F0 to */SLICE_130.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_704
CTOF_DEL    ---     0.238 */SLICE_130.A1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_703.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_703.B0 to */SLICE_703.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_703
ROUTE         1   e 0.908 */SLICE_703.F0 to */SLICE_130.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_704
CTOF_DEL    ---     0.238 */SLICE_130.A1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_702.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_702.B0 to */SLICE_702.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_702
ROUTE         1   e 0.908 */SLICE_702.F0 to */SLICE_130.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_688
CTOF_DEL    ---     0.238 */SLICE_130.A0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_702.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_702.B0 to */SLICE_702.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_702
ROUTE         1   e 0.908 */SLICE_702.F0 to */SLICE_130.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_688
CTOF_DEL    ---     0.238 */SLICE_130.A0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_701.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_701.B0 to */SLICE_701.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_701
ROUTE         1   e 0.908 */SLICE_701.F0 to */SLICE_129.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_672
CTOF_DEL    ---     0.238 */SLICE_129.A1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_701.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_701.B0 to */SLICE_701.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_701
ROUTE         1   e 0.908 */SLICE_701.F0 to */SLICE_129.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_672
CTOF_DEL    ---     0.238 */SLICE_129.A1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_700.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_700.B0 to */SLICE_700.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_700
ROUTE         1   e 0.908 */SLICE_700.F0 to */SLICE_129.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_656
CTOF_DEL    ---     0.238 */SLICE_129.A0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_700.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_700.B0 to */SLICE_700.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_700
ROUTE         1   e 0.908 */SLICE_700.F0 to */SLICE_129.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_656
CTOF_DEL    ---     0.238 */SLICE_129.A0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_699.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_699.B0 to */SLICE_699.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_699
ROUTE         1   e 0.908 */SLICE_699.F0 to */SLICE_128.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_640
CTOF_DEL    ---     0.238 */SLICE_128.A1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_699.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_699.B0 to */SLICE_699.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_699
ROUTE         1   e 0.908 */SLICE_699.F0 to */SLICE_128.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_640
CTOF_DEL    ---     0.238 */SLICE_128.A1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_698.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_698.B0 to */SLICE_698.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_698
ROUTE         1   e 0.908 */SLICE_698.F0 to */SLICE_128.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_624
CTOF_DEL    ---     0.238 */SLICE_128.A0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_698.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_698.B0 to */SLICE_698.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_698
ROUTE         1   e 0.908 */SLICE_698.F0 to */SLICE_128.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_624
CTOF_DEL    ---     0.238 */SLICE_128.A0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_697.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_697.B0 to */SLICE_697.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_697
ROUTE         1   e 0.908 */SLICE_697.F0 to */SLICE_127.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_608
CTOF_DEL    ---     0.238 */SLICE_127.A1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_697.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_697.B0 to */SLICE_697.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_697
ROUTE         1   e 0.908 */SLICE_697.F0 to */SLICE_127.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_608
CTOF_DEL    ---     0.238 */SLICE_127.A1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_696.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_696.B0 to */SLICE_696.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_696
ROUTE         1   e 0.908 */SLICE_696.F0 to */SLICE_127.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_592
CTOF_DEL    ---     0.238 */SLICE_127.A0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_696.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_696.B0 to */SLICE_696.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_696
ROUTE         1   e 0.908 */SLICE_696.F0 to */SLICE_127.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_592
CTOF_DEL    ---     0.238 */SLICE_127.A0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_695.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_695.B0 to */SLICE_695.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_695
ROUTE         1   e 0.908 */SLICE_695.F0 to */SLICE_126.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_576
CTOF_DEL    ---     0.238 */SLICE_126.A1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_695.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_695.B0 to */SLICE_695.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_695
ROUTE         1   e 0.908 */SLICE_695.F0 to */SLICE_126.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_576
CTOF_DEL    ---     0.238 */SLICE_126.A1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_694.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_694.B0 to */SLICE_694.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_694
ROUTE         1   e 0.908 */SLICE_694.F0 to */SLICE_126.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_560
CTOF_DEL    ---     0.238 */SLICE_126.A0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_694.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_694.B0 to */SLICE_694.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_694
ROUTE         1   e 0.908 */SLICE_694.F0 to */SLICE_126.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_560
CTOF_DEL    ---     0.238 */SLICE_126.A0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_693.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_693.B0 to */SLICE_693.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_693
ROUTE         1   e 0.908 */SLICE_693.F0 to */SLICE_125.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_544
CTOF_DEL    ---     0.238 */SLICE_125.A1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_693.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_693.B0 to */SLICE_693.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_693
ROUTE         1   e 0.908 */SLICE_693.F0 to */SLICE_125.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_544
CTOF_DEL    ---     0.238 */SLICE_125.A1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_616.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_616.B1 to */SLICE_616.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F1 to */SLICE_125.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_82
CTOF_DEL    ---     0.238 */SLICE_125.A0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_616.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_616.B1 to */SLICE_616.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F1 to */SLICE_125.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_82
CTOF_DEL    ---     0.238 */SLICE_125.A0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_553.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_553.D0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_553.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_553.D0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_553.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_553.D0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_553.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_553.D0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_692.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_692.B0 to */SLICE_692.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_692
ROUTE         1   e 0.908 */SLICE_692.F0 to */SLICE_124.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_512
CTOF_DEL    ---     0.238 */SLICE_124.A1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_692.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_692.B0 to */SLICE_692.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_692
ROUTE         1   e 0.908 */SLICE_692.F0 to */SLICE_124.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_512
CTOF_DEL    ---     0.238 */SLICE_124.A1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_552.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_552.D0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_552.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_552.D0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_552.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_552.D0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_540.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_540.A0 to */SLICE_540.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 0.908 */SLICE_540.F0 to */SLICE_308.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.238 */SLICE_308.C1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_117.Q0 to */SLICE_640.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]
CTOF_DEL    ---     0.238 */SLICE_640.C1 to */SLICE_640.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_640
ROUTE         1   e 0.908 */SLICE_640.F1 to */SLICE_559.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
CTOF_DEL    ---     0.238 */SLICE_559.C0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_609.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_609.A0 to */SLICE_609.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F0 to */SLICE_308.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.238 */SLICE_308.C0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_680.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_680.B0 to */SLICE_680.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_680
ROUTE         1   e 0.908 */SLICE_680.F0 to */SLICE_118.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_304
CTOF_DEL    ---     0.238 */SLICE_118.A0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_680.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_680.B0 to */SLICE_680.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_680
ROUTE         1   e 0.908 */SLICE_680.F0 to */SLICE_118.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_304
CTOF_DEL    ---     0.238 */SLICE_118.A0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_118.CLK to */SLICE_118.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_118.Q0 to */SLICE_558.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]
CTOF_DEL    ---     0.238 */SLICE_558.C0 to */SLICE_558.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_558
ROUTE         1   e 0.908 */SLICE_558.F0 to */SLICE_537.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1030
CTOF_DEL    ---     0.238 */SLICE_537.B0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_154.CLK to */SLICE_154.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_154.Q1 to */SLICE_640.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]
CTOF_DEL    ---     0.238 */SLICE_640.D1 to */SLICE_640.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_640
ROUTE         1   e 0.908 */SLICE_640.F1 to */SLICE_559.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
CTOF_DEL    ---     0.238 */SLICE_559.C0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_640.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_640.B1 to */SLICE_640.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_640
ROUTE         1   e 0.908 */SLICE_640.F1 to */SLICE_559.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
CTOF_DEL    ---     0.238 */SLICE_559.C0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_675.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_675.A0 to */SLICE_675.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_675
ROUTE         1   e 0.908 */SLICE_675.F0 to */SLICE_505.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[2]
CTOF_DEL    ---     0.238 */SLICE_505.C1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_675.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_675.B0 to */SLICE_675.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_675
ROUTE         1   e 0.908 */SLICE_675.F0 to */SLICE_505.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[2]
CTOF_DEL    ---     0.238 */SLICE_505.C1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_609.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_609.A1 to */SLICE_609.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F1 to */SLICE_307.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.238 */SLICE_307.C1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_542.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_542.D0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_542.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_542.D0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_542.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_542.D0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_682.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_682.B0 to */SLICE_682.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_682
ROUTE         1   e 0.908 */SLICE_682.F0 to */SLICE_119.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_336
CTOF_DEL    ---     0.238 */SLICE_119.A0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_682.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_682.B0 to */SLICE_682.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_682
ROUTE         1   e 0.908 */SLICE_682.F0 to */SLICE_119.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_336
CTOF_DEL    ---     0.238 */SLICE_119.A0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_104.CLK to */SLICE_104.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_104.Q0 to */SLICE_557.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc
CTOF_DEL    ---     0.238 */SLICE_557.A0 to */SLICE_557.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.908 */SLICE_557.F0 to */SLICE_537.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_69
CTOF_DEL    ---     0.238 */SLICE_537.A0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_546.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_546.D0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_546.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_546.D0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_546.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_546.D0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_687.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_687.B0 to */SLICE_687.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_687
ROUTE         1   e 0.908 */SLICE_687.F0 to */SLICE_121.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_416
CTOF_DEL    ---     0.238 */SLICE_121.A1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_545.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_545.D0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_545.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_545.D0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_545.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_545.D0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_544.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_544.D0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_544.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_544.D0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_544.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_544.D0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_543.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_543.D0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_543.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_543.D0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_543.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_543.D0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_686.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_686.B0 to */SLICE_686.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_686
ROUTE         1   e 0.908 */SLICE_686.F0 to */SLICE_121.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_400
CTOF_DEL    ---     0.238 */SLICE_121.A0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_686.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_686.B0 to */SLICE_686.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_686
ROUTE         1   e 0.908 */SLICE_686.F0 to */SLICE_121.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_400
CTOF_DEL    ---     0.238 */SLICE_121.A0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_685.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_685.B0 to */SLICE_685.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_685
ROUTE         1   e 0.908 */SLICE_685.F0 to */SLICE_120.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_384
CTOF_DEL    ---     0.238 */SLICE_120.A1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_685.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_685.B0 to */SLICE_685.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_685
ROUTE         1   e 0.908 */SLICE_685.F0 to */SLICE_120.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_384
CTOF_DEL    ---     0.238 */SLICE_120.A1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_684.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_684.B0 to */SLICE_684.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_684
ROUTE         1   e 0.908 */SLICE_684.F0 to */SLICE_120.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_368
CTOF_DEL    ---     0.238 */SLICE_120.A0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_684.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_684.B0 to */SLICE_684.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_684
ROUTE         1   e 0.908 */SLICE_684.F0 to */SLICE_120.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_368
CTOF_DEL    ---     0.238 */SLICE_120.A0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_683.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_683.B0 to */SLICE_683.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_683
ROUTE         1   e 0.908 */SLICE_683.F0 to */SLICE_119.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_352
CTOF_DEL    ---     0.238 */SLICE_119.A1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_683.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_683.B0 to */SLICE_683.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_683
ROUTE         1   e 0.908 */SLICE_683.F0 to */SLICE_119.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_352
CTOF_DEL    ---     0.238 */SLICE_119.A1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_549.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_549.D0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_507.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_507.B0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_507.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_507.A0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_507.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_507.B0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_165 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_165.CLK to */SLICE_165.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_165 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_165.Q1 to */SLICE_640.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[3]
CTOF_DEL    ---     0.238 */SLICE_640.A1 to */SLICE_640.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_640
ROUTE         1   e 0.908 */SLICE_640.F1 to */SLICE_559.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[2]
CTOF_DEL    ---     0.238 */SLICE_559.C0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_703.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_703.B0 to */SLICE_703.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_703
ROUTE         1   e 0.908 */SLICE_703.F0 to */SLICE_130.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_704
CTOF_DEL    ---     0.238 */SLICE_130.A1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_701.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_701.B0 to */SLICE_701.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_701
ROUTE         1   e 0.908 */SLICE_701.F0 to */SLICE_129.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_672
CTOF_DEL    ---     0.238 */SLICE_129.A1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_699.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_699.B0 to */SLICE_699.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_699
ROUTE         1   e 0.908 */SLICE_699.F0 to */SLICE_128.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_640
CTOF_DEL    ---     0.238 */SLICE_128.A1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_617.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_617.A1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_697.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_697.B0 to */SLICE_697.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_697
ROUTE         1   e 0.908 */SLICE_697.F0 to */SLICE_127.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_608
CTOF_DEL    ---     0.238 */SLICE_127.A1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_716.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_716.B0 to */SLICE_716.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_716
ROUTE         1   e 0.908 */SLICE_716.F0 to */SLICE_138.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_960
CTOF_DEL    ---     0.238 */SLICE_138.A1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_695.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_695.B0 to */SLICE_695.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_695
ROUTE         1   e 0.908 */SLICE_695.F0 to */SLICE_126.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_576
CTOF_DEL    ---     0.238 */SLICE_126.A1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_716.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_716.B0 to */SLICE_716.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_716
ROUTE         1   e 0.908 */SLICE_716.F0 to */SLICE_138.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_960
CTOF_DEL    ---     0.238 */SLICE_138.A1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_693.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_693.B0 to */SLICE_693.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_693
ROUTE         1   e 0.908 */SLICE_693.F0 to */SLICE_125.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_544
CTOF_DEL    ---     0.238 */SLICE_125.A1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_713.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_713.B0 to */SLICE_713.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_713
ROUTE         1   e 0.908 */SLICE_713.F0 to */SLICE_137.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_912
CTOF_DEL    ---     0.238 */SLICE_137.A0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_553.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_553.D0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_711.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_711.B0 to */SLICE_711.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_711
ROUTE         1   e 0.908 */SLICE_711.F0 to */SLICE_136.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_880
CTOF_DEL    ---     0.238 */SLICE_136.A0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_553.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_553.D0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_713.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_713.B0 to */SLICE_713.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_713
ROUTE         1   e 0.908 */SLICE_713.F0 to */SLICE_137.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_912
CTOF_DEL    ---     0.238 */SLICE_137.A0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_692.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_692.B0 to */SLICE_692.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_692
ROUTE         1   e 0.908 */SLICE_692.F0 to */SLICE_124.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_512
CTOF_DEL    ---     0.238 */SLICE_124.A1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_711.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_711.B0 to */SLICE_711.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_711
ROUTE         1   e 0.908 */SLICE_711.F0 to */SLICE_136.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_880
CTOF_DEL    ---     0.238 */SLICE_136.A0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_727.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_727.A0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_552.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_552.D0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_714.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_714.B0 to */SLICE_714.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_714
ROUTE         1   e 0.908 */SLICE_714.F0 to */SLICE_137.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_928
CTOF_DEL    ---     0.238 */SLICE_137.A1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_680.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_680.B0 to */SLICE_680.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_680
ROUTE         1   e 0.908 */SLICE_680.F0 to */SLICE_118.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_304
CTOF_DEL    ---     0.238 */SLICE_118.A0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_714.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_714.B0 to */SLICE_714.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_714
ROUTE         1   e 0.908 */SLICE_714.F0 to */SLICE_137.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_928
CTOF_DEL    ---     0.238 */SLICE_137.A1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_307.CLK to */SLICE_307.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (from jtaghub16_jtck)
ROUTE        28   e 0.908 */SLICE_307.Q0 to */SLICE_557.B0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[0]
CTOF_DEL    ---     0.238 */SLICE_557.B0 to */SLICE_557.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_557
ROUTE         1   e 0.908 */SLICE_557.F0 to */SLICE_537.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_69
CTOF_DEL    ---     0.238 */SLICE_537.A0 to */SLICE_537.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_537
ROUTE         2   e 0.908 */SLICE_537.F0 to */SLICE_566.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jtdo_iv_0_1
CTOF_DEL    ---     0.238 */SLICE_566.B1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_712.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_712.B0 to */SLICE_712.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_712
ROUTE         1   e 0.908 */SLICE_712.F0 to */SLICE_136.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_896
CTOF_DEL    ---     0.238 */SLICE_136.A1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_629.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_629.A1 to */SLICE_629.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F1 to */SLICE_307.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.238 */SLICE_307.C0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_715.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_715.B0 to */SLICE_715.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_715
ROUTE         1   e 0.908 */SLICE_715.F0 to */SLICE_138.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_944
CTOF_DEL    ---     0.238 */SLICE_138.A0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_535.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_535.B1 to */SLICE_535.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_535
ROUTE         2   e 0.908 */SLICE_535.F1 to */SLICE_528.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_sn_N_3
CTOF_DEL    ---     0.238 */SLICE_528.D1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_715.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_715.B0 to */SLICE_715.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_715
ROUTE         1   e 0.908 */SLICE_715.F0 to */SLICE_138.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_944
CTOF_DEL    ---     0.238 */SLICE_138.A0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_504.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_504.A0 to */SLICE_504.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_504
ROUTE         4   e 0.908 */SLICE_504.F0 to */SLICE_505.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_te
CTOF_DEL    ---     0.238 */SLICE_505.D1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_710.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_710.B0 to */SLICE_710.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_710
ROUTE         1   e 0.908 */SLICE_710.F0 to */SLICE_135.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_864
CTOF_DEL    ---     0.238 */SLICE_135.A1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_681.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_681.B0 to */SLICE_681.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_681
ROUTE         1   e 0.908 */SLICE_681.F0 to */SLICE_118.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_320
CTOF_DEL    ---     0.238 */SLICE_118.A1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_709.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_709.B0 to */SLICE_709.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_709
ROUTE         1   e 0.908 */SLICE_709.F0 to */SLICE_134.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_832
CTOF_DEL    ---     0.238 */SLICE_134.A1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_542.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_542.D0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_710.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_710.B0 to */SLICE_710.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_710
ROUTE         1   e 0.908 */SLICE_710.F0 to */SLICE_135.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_864
CTOF_DEL    ---     0.238 */SLICE_135.A1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_682.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_682.B0 to */SLICE_682.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_682
ROUTE         1   e 0.908 */SLICE_682.F0 to */SLICE_119.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_336
CTOF_DEL    ---     0.238 */SLICE_119.A0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_709.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_709.B0 to */SLICE_709.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_709
ROUTE         1   e 0.908 */SLICE_709.F0 to */SLICE_134.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_832
CTOF_DEL    ---     0.238 */SLICE_134.A1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_552.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_552.D0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_708.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_708.B0 to */SLICE_708.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_708
ROUTE         1   e 0.908 */SLICE_708.F0 to */SLICE_134.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_816
CTOF_DEL    ---     0.238 */SLICE_134.A0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_551.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_551.D0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_712.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_712.B0 to */SLICE_712.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_712
ROUTE         1   e 0.908 */SLICE_712.F0 to */SLICE_136.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_896
CTOF_DEL    ---     0.238 */SLICE_136.A1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_549.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_549.D0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_708.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_708.B0 to */SLICE_708.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_708
ROUTE         1   e 0.908 */SLICE_708.F0 to */SLICE_134.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_816
CTOF_DEL    ---     0.238 */SLICE_134.A0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_549.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_549.D0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_707.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_707.B0 to */SLICE_707.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_707
ROUTE         1   e 0.908 */SLICE_707.F0 to */SLICE_133.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_800
CTOF_DEL    ---     0.238 */SLICE_133.A1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_689.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_689.B0 to */SLICE_689.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_689
ROUTE         1   e 0.908 */SLICE_689.F0 to */SLICE_122.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_448
CTOF_DEL    ---     0.238 */SLICE_122.A1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_707.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_707.B0 to */SLICE_707.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_707
ROUTE         1   e 0.908 */SLICE_707.F0 to */SLICE_133.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_800
CTOF_DEL    ---     0.238 */SLICE_133.A1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_548.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_548.D0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_678.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_678.B0 to */SLICE_678.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_678
ROUTE         1   e 0.908 */SLICE_678.F0 to */SLICE_133.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_784
CTOF_DEL    ---     0.238 */SLICE_133.A0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_547.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_547.D0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_678.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_678.B0 to */SLICE_678.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_678
ROUTE         1   e 0.908 */SLICE_678.F0 to */SLICE_133.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_784
CTOF_DEL    ---     0.238 */SLICE_133.A0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_546.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_546.D0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_679.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_679.B0 to */SLICE_679.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_679
ROUTE         1   e 0.908 */SLICE_679.F0 to */SLICE_132.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_768
CTOF_DEL    ---     0.238 */SLICE_132.A1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_684.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_684.B0 to */SLICE_684.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_684
ROUTE         1   e 0.908 */SLICE_684.F0 to */SLICE_120.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_368
CTOF_DEL    ---     0.238 */SLICE_120.A0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_679.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_679.B0 to */SLICE_679.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_679
ROUTE         1   e 0.908 */SLICE_679.F0 to */SLICE_132.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_768
CTOF_DEL    ---     0.238 */SLICE_132.A1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_542.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_542.D0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_706.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_706.B0 to */SLICE_706.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_706
ROUTE         1   e 0.908 */SLICE_706.F0 to */SLICE_132.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_752
CTOF_DEL    ---     0.238 */SLICE_132.A0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_551.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_551.D0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_706.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_706.B0 to */SLICE_706.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_706
ROUTE         1   e 0.908 */SLICE_706.F0 to */SLICE_132.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_752
CTOF_DEL    ---     0.238 */SLICE_132.A0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_691.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_691.B0 to */SLICE_691.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_691
ROUTE         1   e 0.908 */SLICE_691.F0 to */SLICE_124.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_496
CTOF_DEL    ---     0.238 */SLICE_124.A0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_507.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_507.A0 to */SLICE_507.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_507
ROUTE         2   e 0.908 */SLICE_507.F0 to */SLICE_477.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_3[1]
CTOF_DEL    ---     0.238 */SLICE_477.D0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.908 */SLICE_539.F1 to */SLICE_550.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_550.D0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_600.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_600.A0 to */SLICE_600.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_600
ROUTE         1   e 0.908 */SLICE_600.F0 to */SLICE_477.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/wen_te_1_0_a3_0[0]
CTOF_DEL    ---     0.238 */SLICE_477.C0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_477.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_477.B1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.908 */SLICE_477.F1 to */SLICE_506.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_506.A0 to */SLICE_506.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_506
ROUTE         4   e 0.908 */SLICE_506.F0 to */SLICE_526.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[1]
CTOF_DEL    ---     0.238 */SLICE_526.D0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    5.025ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (4.948ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_712.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_712.B0 to */SLICE_712.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_712
ROUTE         1   e 0.908 */SLICE_712.F0 to */SLICE_136.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_896
CTOF_DEL    ---     0.238 */SLICE_136.A1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    4.948   (26.6% logic, 73.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_670.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_670.C0 to */SLICE_670.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_670
ROUTE         1   e 0.908 */SLICE_670.F0 to */SLICE_526.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr38_3
CTOF_DEL    ---     0.238 */SLICE_526.C0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_287.CLK to */SLICE_287.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_287.Q0 to */SLICE_521.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_enz
CTOF_DEL    ---     0.238 */SLICE_521.A1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_145.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_144.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_143.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_142.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_148.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_147.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_146.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to */SLICE_670.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_670.B0 to */SLICE_670.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_670
ROUTE         1   e 0.908 */SLICE_670.F0 to */SLICE_526.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr38_3
CTOF_DEL    ---     0.238 */SLICE_526.C0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_148.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_147.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_146.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_145.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_144.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_143.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_142.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_141.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_191.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_191.C1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_466.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_466.A0 to */SLICE_466.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_466
ROUTE         1   e 0.908 */SLICE_466.F0 to */SLICE_555.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_4_i_0_1
CTOF_DEL    ---     0.238 */SLICE_555.D0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_141.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_525.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_525.C0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_524.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_524.B0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.935ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (4.709ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_514.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_514.B0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    4.709   (22.9% logic, 77.1% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    4.819ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.742ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_511.CLK to */SLICE_511.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511 (from ipClk_c)
ROUTE         5   e 0.232 */SLICE_511.Q0 to */SLICE_511.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]
CTOF_DEL    ---     0.238 */SLICE_511.B0 to */SLICE_511.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511
ROUTE         1   e 0.232 */SLICE_511.F0 to */SLICE_511.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tu[0][2]
CTOF_DEL    ---     0.238 */SLICE_511.C1 to */SLICE_511.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_511
ROUTE         1   e 0.908 */SLICE_511.F1 to */SLICE_505.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_trig_N_2L1
CTOF_DEL    ---     0.238 */SLICE_505.B1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.742   (32.7% logic, 67.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.729ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.503ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_615.Q0 to */SLICE_615.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_615.C1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.503   (29.2% logic, 70.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.729ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.503ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_615.Q0 to */SLICE_615.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_615.C1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.503   (29.2% logic, 70.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.729ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.503ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_615.Q0 to */SLICE_615.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_615.C1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.503   (29.2% logic, 70.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.729ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (4.503ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_521.Q0 to */SLICE_521.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_521.A0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_524.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_524.D0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    4.503   (29.2% logic, 70.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.729ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (4.503ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_615.Q0 to */SLICE_615.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_615.C1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.503   (29.2% logic, 70.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.354ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (4.277ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_479.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_479.B0 to */SLICE_479.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_479
ROUTE         1   e 0.232 */SLICE_479.F0 to */SLICE_479.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_4_0_0_1
CTOF_DEL    ---     0.238 */SLICE_479.A1 to */SLICE_479.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_479
ROUTE         2   e 0.908 */SLICE_479.F1 to */SLICE_627.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g1_1
CTOF_DEL    ---     0.238 */SLICE_627.A0 to */SLICE_627.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_627
ROUTE         1   e 0.908 */SLICE_627.F0 to */SLICE_104.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_1_sn
MTOOFX_DEL  ---     0.243 */SLICE_104.M0 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    4.277   (30.9% logic, 69.1% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q0 to */SLICE_521.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_521.C0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_477.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_477.B1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q1 to */SLICE_521.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_521.D0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q0 to */SLICE_521.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_521.C0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q1 to */SLICE_521.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_521.D0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.232 */SLICE_556.F1 to */SLICE_556.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_556.B0 to */SLICE_556.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE         1   e 0.908 */SLICE_556.F0 to */SLICE_135.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_848
CTOF_DEL    ---     0.238 */SLICE_135.A0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.232 */SLICE_556.F1 to */SLICE_556.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_556.B0 to */SLICE_556.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE         1   e 0.908 */SLICE_556.F0 to */SLICE_135.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_848
CTOF_DEL    ---     0.238 */SLICE_135.A0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_552.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_552.A0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_550.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_550.A0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_477.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_477.C1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.232 */SLICE_556.F1 to */SLICE_556.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_556.B0 to */SLICE_556.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE         1   e 0.908 */SLICE_556.F0 to */SLICE_135.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_848
CTOF_DEL    ---     0.238 */SLICE_135.A0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_314.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_314.A1 to */SLICE_314.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.232 */SLICE_314.F1 to */SLICE_314.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.238 */SLICE_314.C0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_551.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_551.A0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_549.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_549.A0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_111.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_111.C1 to */SLICE_111.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE        17   e 0.908 */SLICE_111.F1 to */SLICE_541.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_55
CTOF_DEL    ---     0.238 */SLICE_541.A1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.232 */SLICE_541.F1 to */SLICE_541.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_541.A0 to */SLICE_541.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE         1   e 0.908 */SLICE_541.F0 to */SLICE_311.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.238 */SLICE_311.C1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_546.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_546.A0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_544.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_544.A0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_154.CLK to */SLICE_154.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_154.Q0 to */SLICE_640.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]
CTOF_DEL    ---     0.238 */SLICE_640.D0 to */SLICE_640.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_640
ROUTE         1   e 0.908 */SLICE_640.F0 to */SLICE_481.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
CTOF_DEL    ---     0.238 */SLICE_481.A1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_477.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_477.B1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_477.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_477.A1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_521.B0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_521.B0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_542.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_542.A0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_73.Q1 to */SLICE_604.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[3]
CTOF_DEL    ---     0.238 */SLICE_604.A1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.232 */SLICE_539.F1 to */SLICE_539.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_539.C0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_153.CLK to */SLICE_153.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_153.Q1 to */SLICE_641.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]
CTOF_DEL    ---     0.238 */SLICE_641.D0 to */SLICE_641.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F0 to */SLICE_478.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
CTOF_DEL    ---     0.238 */SLICE_478.A1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.232 */SLICE_195.F1 to */SLICE_195.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_195.C0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_165 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_165.CLK to */SLICE_165.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_165 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_165.Q0 to */SLICE_640.A0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[2]
CTOF_DEL    ---     0.238 */SLICE_640.A0 to */SLICE_640.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_640
ROUTE         1   e 0.908 */SLICE_640.F0 to */SLICE_481.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
CTOF_DEL    ---     0.238 */SLICE_481.A1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_244 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_244.CLK to */SLICE_244.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_244 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_244.Q0 to */SLICE_559.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]
CTOF_DEL    ---     0.238 */SLICE_559.C1 to */SLICE_559.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.232 */SLICE_559.F1 to */SLICE_559.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[3]
CTOF_DEL    ---     0.238 */SLICE_559.B0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_278 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_278.CLK to */SLICE_278.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_278 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_278.Q1 to */SLICE_528.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]
CTOF_DEL    ---     0.238 */SLICE_528.A0 to */SLICE_528.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.232 */SLICE_528.F0 to */SLICE_528.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][1]
CTOF_DEL    ---     0.238 */SLICE_528.B1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_164 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_164.CLK to */SLICE_164.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_164 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_164.Q0 to */SLICE_564.A0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[0]
CTOF_DEL    ---     0.238 */SLICE_564.A0 to */SLICE_564.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_564
ROUTE         3   e 0.908 */SLICE_564.F0 to */SLICE_566.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_m6_i_a3_N_2_1_0
CTOF_DEL    ---     0.238 */SLICE_566.A0 to */SLICE_566.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         2   e 0.232 */SLICE_566.F0 to */SLICE_566.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_N_6_0
CTOF_DEL    ---     0.238 */SLICE_566.A1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_477.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_477.A1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.232 */SLICE_195.F1 to */SLICE_195.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_195.C0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.232 */SLICE_195.F1 to */SLICE_195.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_195.C0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_675 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_675.CLK to */SLICE_675.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_675 (from ipClk_c)
ROUTE         2   e 0.232 */SLICE_675.Q0 to */SLICE_675.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]
CTOF_DEL    ---     0.238 */SLICE_675.D0 to */SLICE_675.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/SLICE_675
ROUTE         1   e 0.908 */SLICE_675.F0 to */SLICE_505.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_tcnt[2]
CTOF_DEL    ---     0.238 */SLICE_505.C1 to */SLICE_505.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_505
ROUTE         1   e 0.908 */SLICE_505.F1 to */SLICE_481.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[2]
CTOF_DEL    ---     0.238 */SLICE_481.B0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_283 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_283.CLK to */SLICE_283.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_283 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_283.Q1 to */SLICE_528.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]
CTOF_DEL    ---     0.238 */SLICE_528.D0 to */SLICE_528.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.232 */SLICE_528.F0 to */SLICE_528.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/rd_dout_te[1][1]
CTOF_DEL    ---     0.238 */SLICE_528.B1 to */SLICE_528.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_528
ROUTE         1   e 0.908 */SLICE_528.F1 to */SLICE_478.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[1]
CTOF_DEL    ---     0.238 */SLICE_478.B0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_164 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_164.CLK to */SLICE_164.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_164 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_164.Q1 to */SLICE_641.A0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[1]
CTOF_DEL    ---     0.238 */SLICE_641.A0 to */SLICE_641.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F0 to */SLICE_478.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
CTOF_DEL    ---     0.238 */SLICE_478.A1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.232 */SLICE_195.F1 to */SLICE_195.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_195.C0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_153.CLK to */SLICE_153.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_153.Q0 to */SLICE_564.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]
CTOF_DEL    ---     0.238 */SLICE_564.D0 to */SLICE_564.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_564
ROUTE         3   e 0.908 */SLICE_564.F0 to */SLICE_566.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_m6_i_a3_N_2_1_0
CTOF_DEL    ---     0.238 */SLICE_566.A0 to */SLICE_566.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         2   e 0.232 */SLICE_566.F0 to */SLICE_566.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_N_6_0
CTOF_DEL    ---     0.238 */SLICE_566.A1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_641.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_641.B0 to */SLICE_641.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F0 to */SLICE_478.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
CTOF_DEL    ---     0.238 */SLICE_478.A1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_640.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_640.B0 to */SLICE_640.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_640
ROUTE         1   e 0.908 */SLICE_640.F0 to */SLICE_481.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
CTOF_DEL    ---     0.238 */SLICE_481.A1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_641.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_641.C0 to */SLICE_641.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F0 to */SLICE_478.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[0]
CTOF_DEL    ---     0.238 */SLICE_478.A1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q1 to */SLICE_727.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]
CTOF_DEL    ---     0.238 */SLICE_727.D0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.232 */SLICE_539.F1 to */SLICE_539.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_539.C0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_640.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_640.C0 to */SLICE_640.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_640
ROUTE         1   e 0.908 */SLICE_640.F0 to */SLICE_481.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[1]
CTOF_DEL    ---     0.238 */SLICE_481.A1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_604.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8]
CTOF_DEL    ---     0.238 */SLICE_604.B1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.232 */SLICE_539.F1 to */SLICE_539.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_539.C0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_604.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_604.D1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.232 */SLICE_539.F1 to */SLICE_539.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_539.C0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.232 */SLICE_556.F1 to */SLICE_556.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_556.B0 to */SLICE_556.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE         1   e 0.908 */SLICE_556.F0 to */SLICE_135.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_848
CTOF_DEL    ---     0.238 */SLICE_135.A0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_553.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_553.A0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_548.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_548.A0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_547.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_547.A0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_545.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_545.A0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.232 */SLICE_561.F1 to */SLICE_561.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_561.A0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_543.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_543.A0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to */SLICE_604.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10]
CTOF_DEL    ---     0.238 */SLICE_604.C1 to */SLICE_604.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_604
ROUTE         1   e 0.908 */SLICE_604.F1 to */SLICE_539.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_4
CTOF_DEL    ---     0.238 */SLICE_539.D1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.232 */SLICE_539.F1 to */SLICE_539.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_539.C0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_116.CLK to */SLICE_116.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_116.Q0 to */SLICE_727.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]
CTOF_DEL    ---     0.238 */SLICE_727.C0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.232 */SLICE_539.F1 to */SLICE_539.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_539.C0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_559.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_559.D1 to */SLICE_559.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.232 */SLICE_559.F1 to */SLICE_559.B0 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_trig[3]
CTOF_DEL    ---     0.238 */SLICE_559.B0 to */SLICE_559.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_559
ROUTE         1   e 0.908 */SLICE_559.F0 to */SLICE_539.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1[2]
CTOF_DEL    ---     0.238 */SLICE_539.A0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_521.B0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_521.B0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.908 *u/SLICE_76.Q1 to */SLICE_727.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9]
CTOF_DEL    ---     0.238 */SLICE_727.B0 to */SLICE_727.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_727
ROUTE         1   e 0.908 */SLICE_727.F0 to */SLICE_539.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_0_a2_1
CTOF_DEL    ---     0.238 */SLICE_539.C1 to */SLICE_539.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE        21   e 0.232 */SLICE_539.F1 to */SLICE_539.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un5_jtdo_first_bit_sn
CTOF_DEL    ---     0.238 */SLICE_539.C0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_525.Q0 to */SLICE_525.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_525.B1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_617.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_617.B1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.232 */SLICE_513.F1 to */SLICE_513.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_513.A0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (4.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q1 to */SLICE_477.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[11]
CTOF_DEL    ---     0.238 */SLICE_477.C1 to */SLICE_477.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         4   e 0.232 */SLICE_477.F1 to */SLICE_477.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/N_25
CTOF_DEL    ---     0.238 */SLICE_477.A0 to */SLICE_477.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/decode_u/SLICE_477
ROUTE         5   e 0.908 */SLICE_477.F0 to */SLICE_517.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/wen_te[0]
CTOF_DEL    ---     0.238 */SLICE_517.D0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    4.272   (30.8% logic, 69.2% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_602.C0 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_602.C0 to */SLICE_602.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602
ROUTE         1   e 0.908 */SLICE_602.F0 to */SLICE_527.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen_2
CTOF_DEL    ---     0.238 */SLICE_527.C1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_615.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_615.A1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_520.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_520.A1 to */SLICE_520.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.232 */SLICE_520.F1 to */SLICE_520.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_2
CTOF_DEL    ---     0.238 */SLICE_520.C0 to */SLICE_520.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.908 */SLICE_520.F0 to */SLICE_516.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_3_0
CTOF_DEL    ---     0.238 */SLICE_516.B0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_615.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_615.B1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to */SLICE_520.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_520.B1 to */SLICE_520.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.232 */SLICE_520.F1 to */SLICE_520.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_2
CTOF_DEL    ---     0.238 */SLICE_520.C0 to */SLICE_520.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.908 */SLICE_520.F0 to */SLICE_516.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_3_0
CTOF_DEL    ---     0.238 */SLICE_516.B0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_520.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_520.C1 to */SLICE_520.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.232 */SLICE_520.F1 to */SLICE_520.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_2
CTOF_DEL    ---     0.238 */SLICE_520.C0 to */SLICE_520.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.908 */SLICE_520.F0 to */SLICE_516.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_3_0
CTOF_DEL    ---     0.238 */SLICE_516.B0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_520.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_520.D1 to */SLICE_520.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.232 */SLICE_520.F1 to */SLICE_520.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_2
CTOF_DEL    ---     0.238 */SLICE_520.C0 to */SLICE_520.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.908 */SLICE_520.F0 to */SLICE_516.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_3_0
CTOF_DEL    ---     0.238 */SLICE_516.B0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q0 to */SLICE_521.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_521.C0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_525.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_525.B0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_516.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_516.B1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_538.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte
CTOF_DEL    ---     0.238 */SLICE_538.A0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_538.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte
CTOF_DEL    ---     0.238 */SLICE_538.A0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_538.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte
CTOF_DEL    ---     0.238 */SLICE_538.A0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q1 to */SLICE_521.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_521.D0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_525.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_525.B0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_516.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_516.C1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_527.D1 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_527.D1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_602.D0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_602.D0 to */SLICE_602.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602
ROUTE         1   e 0.908 */SLICE_602.F0 to */SLICE_527.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen_2
CTOF_DEL    ---     0.238 */SLICE_527.C1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_538.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte
CTOF_DEL    ---     0.238 */SLICE_538.A0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_538.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte
CTOF_DEL    ---     0.238 */SLICE_538.A0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_538.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte
CTOF_DEL    ---     0.238 */SLICE_538.A0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_516.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_516.B1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_516.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_516.B1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_516.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_516.B1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_521.B0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_521.B0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_525.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_525.B0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_602.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_602.A0 to */SLICE_602.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602
ROUTE         1   e 0.908 */SLICE_602.F0 to */SLICE_527.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen_2
CTOF_DEL    ---     0.238 */SLICE_527.C1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_516.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_516.C1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_516.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_516.C1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_516.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_516.C1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.232 */SLICE_523.F1 to */SLICE_523.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_523.A0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    4.259ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (4.033ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_615.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_615.D1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    4.033   (26.7% logic, 73.3% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_670.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_670.C0 to */SLICE_670.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_670
ROUTE         1   e 0.908 */SLICE_670.F0 to */SLICE_526.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr38_3
CTOF_DEL    ---     0.238 */SLICE_526.C0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_670.C0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_670.C0 to */SLICE_670.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_670
ROUTE         1   e 0.908 */SLICE_670.F0 to */SLICE_526.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr38_3
CTOF_DEL    ---     0.238 */SLICE_526.C0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to   SLICE_522.D0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238   SLICE_522.D0 to   SLICE_522.F0 SLICE_522
ROUTE         2   e 0.908   SLICE_522.F0 to */SLICE_517.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/addr_cnt_init_1_2
CTOF_DEL    ---     0.238 */SLICE_517.A0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to   SLICE_522.D0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238   SLICE_522.D0 to   SLICE_522.F0 SLICE_522
ROUTE         2   e 0.908   SLICE_522.F0 to */SLICE_517.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/addr_cnt_init_1_2
CTOF_DEL    ---     0.238 */SLICE_517.A0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_287.CLK to */SLICE_287.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_287.Q0 to */SLICE_521.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_enz
CTOF_DEL    ---     0.238 */SLICE_521.A1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_288.Q1 to */SLICE_289.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_289.C1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_617.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_617.B1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to */SLICE_670.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_670.B0 to */SLICE_670.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_670
ROUTE         1   e 0.908 */SLICE_670.F0 to */SLICE_526.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr38_3
CTOF_DEL    ---     0.238 */SLICE_526.C0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_287.CLK to */SLICE_287.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_287.Q0 to */SLICE_521.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_enz
CTOF_DEL    ---     0.238 */SLICE_521.A1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_553.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_553.A0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_550.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_550.A0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_687.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_687.B0 to */SLICE_687.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_687
ROUTE         1   e 0.908 */SLICE_687.F0 to */SLICE_121.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_416
CTOF_DEL    ---     0.238 */SLICE_121.A1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.B0 to */SLICE_636.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE         1   e 0.908 */SLICE_636.F0 to */SLICE_309.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.238 */SLICE_309.C0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_683.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_683.B0 to */SLICE_683.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_683
ROUTE         1   e 0.908 */SLICE_683.F0 to */SLICE_119.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_352
CTOF_DEL    ---     0.238 */SLICE_119.A1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B0 to */SLICE_151.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to */SLICE_615.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_615.D1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_551.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_551.A0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_717.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_717.B0 to */SLICE_717.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_717
ROUTE         1   e 0.908 */SLICE_717.F0 to */SLICE_123.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_84
CTOF_DEL    ---     0.238 */SLICE_123.A1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_549.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_549.A0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_689.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_689.B0 to */SLICE_689.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_689
ROUTE         1   e 0.908 */SLICE_689.F0 to */SLICE_122.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_448
CTOF_DEL    ---     0.238 */SLICE_122.A1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_547.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_547.A0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_546.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_546.A0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_545.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_545.A0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_607.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_607.B1 to */SLICE_607.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F1 to */SLICE_309.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.238 */SLICE_309.C1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B1 to */SLICE_151.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_615.B1 Test_reveal_coretop_instance/test_la0_inst_0/parity_err
CTOF_DEL    ---     0.238 */SLICE_615.B1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_692.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_692.B0 to */SLICE_692.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_692
ROUTE         1   e 0.908 */SLICE_692.F0 to */SLICE_124.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_512
CTOF_DEL    ---     0.238 */SLICE_124.A1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_681.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_681.B0 to */SLICE_681.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_681
ROUTE         1   e 0.908 */SLICE_681.F0 to */SLICE_118.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_320
CTOF_DEL    ---     0.238 */SLICE_118.A1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B0 to */SLICE_152.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_686.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_686.B0 to */SLICE_686.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_686
ROUTE         1   e 0.908 */SLICE_686.F0 to */SLICE_121.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_400
CTOF_DEL    ---     0.238 */SLICE_121.A0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_542.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_542.A0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_609.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_609.B1 to */SLICE_609.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F1 to */SLICE_307.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.238 */SLICE_307.C1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B0 to */SLICE_152.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_608.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_608.B0 to */SLICE_608.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F0 to */SLICE_313.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.238 */SLICE_313.C0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_605.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_605.B1 to */SLICE_605.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F1 to */SLICE_312.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[11]
CTOF_DEL    ---     0.238 */SLICE_312.C1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_689.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_689.B0 to */SLICE_689.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_689
ROUTE         1   e 0.908 */SLICE_689.F0 to */SLICE_122.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_448
CTOF_DEL    ---     0.238 */SLICE_122.A1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_606.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_606.B1 to */SLICE_606.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F1 to */SLICE_311.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.238 */SLICE_311.C0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_607.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_607.B0 to */SLICE_607.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F0 to */SLICE_310.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[6]
CTOF_DEL    ---     0.238 */SLICE_310.C0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_552.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_552.A0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_548.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_548.A0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_543.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_543.A0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_685.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_685.B0 to */SLICE_685.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_685
ROUTE         1   e 0.908 */SLICE_685.F0 to */SLICE_120.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_384
CTOF_DEL    ---     0.238 */SLICE_120.A1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_540.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_540.A0 to */SLICE_540.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 0.908 */SLICE_540.F0 to */SLICE_308.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.238 */SLICE_308.C1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_608.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_608.A1 to */SLICE_608.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F1 to */SLICE_313.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[13]
CTOF_DEL    ---     0.238 */SLICE_313.C1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_608.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_608.B0 to */SLICE_608.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F0 to */SLICE_313.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.238 */SLICE_313.C0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_605.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_605.A1 to */SLICE_605.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F1 to */SLICE_312.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[11]
CTOF_DEL    ---     0.238 */SLICE_312.C1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_605.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_605.B0 to */SLICE_605.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F0 to */SLICE_312.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.238 */SLICE_312.C0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_541.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_541.B0 to */SLICE_541.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE         1   e 0.908 */SLICE_541.F0 to */SLICE_311.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.238 */SLICE_311.C1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_606.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_606.B1 to */SLICE_606.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F1 to */SLICE_311.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.238 */SLICE_311.C0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_687.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_687.B0 to */SLICE_687.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_687
ROUTE         1   e 0.908 */SLICE_687.F0 to */SLICE_121.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_416
CTOF_DEL    ---     0.238 */SLICE_121.A1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_544.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_544.A0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_680.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_680.B0 to */SLICE_680.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_680
ROUTE         1   e 0.908 */SLICE_680.F0 to */SLICE_118.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_304
CTOF_DEL    ---     0.238 */SLICE_118.A0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B0 to */SLICE_151.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_139.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_139.B0 to */SLICE_139.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_609.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_609.B0 to */SLICE_609.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F0 to */SLICE_308.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.238 */SLICE_308.C0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_680.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_680.B0 to */SLICE_680.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_680
ROUTE         1   e 0.908 */SLICE_680.F0 to */SLICE_118.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_304
CTOF_DEL    ---     0.238 */SLICE_118.A0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B0 to */SLICE_151.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_139.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_139.B0 to */SLICE_139.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_543.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_543.A0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_684.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_684.B0 to */SLICE_684.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_684
ROUTE         1   e 0.908 */SLICE_684.F0 to */SLICE_120.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_368
CTOF_DEL    ---     0.238 */SLICE_120.A0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_682.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_682.B0 to */SLICE_682.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_682
ROUTE         1   e 0.908 */SLICE_682.F0 to */SLICE_119.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_336
CTOF_DEL    ---     0.238 */SLICE_119.A0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_629.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_629.B1 to */SLICE_629.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F1 to */SLICE_307.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.238 */SLICE_307.C0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_608.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_608.B1 to */SLICE_608.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F1 to */SLICE_313.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[13]
CTOF_DEL    ---     0.238 */SLICE_313.C1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_717.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_717.B0 to */SLICE_717.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_717
ROUTE         1   e 0.908 */SLICE_717.F0 to */SLICE_123.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_84
CTOF_DEL    ---     0.238 */SLICE_123.A1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_605.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_605.B0 to */SLICE_605.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F0 to */SLICE_312.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.238 */SLICE_312.C0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_541.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_541.B0 to */SLICE_541.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE         1   e 0.908 */SLICE_541.F0 to */SLICE_311.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.238 */SLICE_311.C1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_606.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_606.B0 to */SLICE_606.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F0 to */SLICE_310.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.238 */SLICE_310.C1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_607.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_607.B1 to */SLICE_607.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F1 to */SLICE_309.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.238 */SLICE_309.C1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_693.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_693.B0 to */SLICE_693.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_693
ROUTE         1   e 0.908 */SLICE_693.F0 to */SLICE_125.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_544
CTOF_DEL    ---     0.238 */SLICE_125.A1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q0 to */SLICE_286.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_286.B1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q1 to */SLICE_286.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_286.D1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q0 to */SLICE_618.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_618.B0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_139.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_139.B0 to */SLICE_139.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_716.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_716.B0 to */SLICE_716.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_716
ROUTE         1   e 0.908 */SLICE_716.F0 to */SLICE_138.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_960
CTOF_DEL    ---     0.238 */SLICE_138.A1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_713.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_713.B0 to */SLICE_713.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_713
ROUTE         1   e 0.908 */SLICE_713.F0 to */SLICE_137.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_912
CTOF_DEL    ---     0.238 */SLICE_137.A0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_711.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_711.B0 to */SLICE_711.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_711
ROUTE         1   e 0.908 */SLICE_711.F0 to */SLICE_136.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_880
CTOF_DEL    ---     0.238 */SLICE_136.A0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_259.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_259.C0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_714.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_714.B0 to */SLICE_714.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_714
ROUTE         1   e 0.908 */SLICE_714.F0 to */SLICE_137.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_928
CTOF_DEL    ---     0.238 */SLICE_137.A1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_712.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_712.B0 to */SLICE_712.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_712
ROUTE         1   e 0.908 */SLICE_712.F0 to */SLICE_136.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_896
CTOF_DEL    ---     0.238 */SLICE_136.A1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_715.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_715.B0 to */SLICE_715.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_715
ROUTE         1   e 0.908 */SLICE_715.F0 to */SLICE_138.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_944
CTOF_DEL    ---     0.238 */SLICE_138.A0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_710.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_710.B0 to */SLICE_710.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_710
ROUTE         1   e 0.908 */SLICE_710.F0 to */SLICE_135.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_864
CTOF_DEL    ---     0.238 */SLICE_135.A1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_709.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_709.B0 to */SLICE_709.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_709
ROUTE         1   e 0.908 */SLICE_709.F0 to */SLICE_134.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_832
CTOF_DEL    ---     0.238 */SLICE_134.A1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_708.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_708.B0 to */SLICE_708.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_708
ROUTE         1   e 0.908 */SLICE_708.F0 to */SLICE_134.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_816
CTOF_DEL    ---     0.238 */SLICE_134.A0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_707.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_707.B0 to */SLICE_707.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_707
ROUTE         1   e 0.908 */SLICE_707.F0 to */SLICE_133.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_800
CTOF_DEL    ---     0.238 */SLICE_133.A1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_678.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_678.B0 to */SLICE_678.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_678
ROUTE         1   e 0.908 */SLICE_678.F0 to */SLICE_133.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_784
CTOF_DEL    ---     0.238 */SLICE_133.A0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_679.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_679.B0 to */SLICE_679.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_679
ROUTE         1   e 0.908 */SLICE_679.F0 to */SLICE_132.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_768
CTOF_DEL    ---     0.238 */SLICE_132.A1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_706.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_706.B0 to */SLICE_706.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_706
ROUTE         1   e 0.908 */SLICE_706.F0 to */SLICE_132.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_752
CTOF_DEL    ---     0.238 */SLICE_132.A0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_705.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_705.B0 to */SLICE_705.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_705
ROUTE         1   e 0.908 */SLICE_705.F0 to */SLICE_131.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_736
CTOF_DEL    ---     0.238 */SLICE_131.A1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_704.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_704.B0 to */SLICE_704.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_704
ROUTE         1   e 0.908 */SLICE_704.F0 to */SLICE_131.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_720
CTOF_DEL    ---     0.238 */SLICE_131.A0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_703.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_703.B0 to */SLICE_703.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_703
ROUTE         1   e 0.908 */SLICE_703.F0 to */SLICE_130.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_704
CTOF_DEL    ---     0.238 */SLICE_130.A1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_702.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_702.B0 to */SLICE_702.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_702
ROUTE         1   e 0.908 */SLICE_702.F0 to */SLICE_130.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_688
CTOF_DEL    ---     0.238 */SLICE_130.A0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_701.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_701.B0 to */SLICE_701.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_701
ROUTE         1   e 0.908 */SLICE_701.F0 to */SLICE_129.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_672
CTOF_DEL    ---     0.238 */SLICE_129.A1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_700.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_700.B0 to */SLICE_700.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_700
ROUTE         1   e 0.908 */SLICE_700.F0 to */SLICE_129.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_656
CTOF_DEL    ---     0.238 */SLICE_129.A0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_699.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_699.B0 to */SLICE_699.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_699
ROUTE         1   e 0.908 */SLICE_699.F0 to */SLICE_128.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_640
CTOF_DEL    ---     0.238 */SLICE_128.A1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_698.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_698.B0 to */SLICE_698.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_698
ROUTE         1   e 0.908 */SLICE_698.F0 to */SLICE_128.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_624
CTOF_DEL    ---     0.238 */SLICE_128.A0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_697.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_697.B0 to */SLICE_697.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_697
ROUTE         1   e 0.908 */SLICE_697.F0 to */SLICE_127.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_608
CTOF_DEL    ---     0.238 */SLICE_127.A1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_696.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_696.B0 to */SLICE_696.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_696
ROUTE         1   e 0.908 */SLICE_696.F0 to */SLICE_127.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_592
CTOF_DEL    ---     0.238 */SLICE_127.A0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_695.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_695.B0 to */SLICE_695.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_695
ROUTE         1   e 0.908 */SLICE_695.F0 to */SLICE_126.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_576
CTOF_DEL    ---     0.238 */SLICE_126.A1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_553.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_553.A0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q1 to */SLICE_619.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]
CTOF_DEL    ---     0.238 */SLICE_619.B0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_692.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_692.B0 to */SLICE_692.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_692
ROUTE         1   e 0.908 */SLICE_692.F0 to */SLICE_124.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_512
CTOF_DEL    ---     0.238 */SLICE_124.A1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_551.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_551.A0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_552.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_552.A0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_549.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_549.A0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_543.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_543.A0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_606.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_606.A0 to */SLICE_606.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F0 to */SLICE_310.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.238 */SLICE_310.C1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_542.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_542.A0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_607.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_607.A0 to */SLICE_607.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F0 to */SLICE_310.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[6]
CTOF_DEL    ---     0.238 */SLICE_310.C0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_609.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_609.A0 to */SLICE_609.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F0 to */SLICE_308.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.238 */SLICE_308.C0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_636.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_636.A0 to */SLICE_636.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE         1   e 0.908 */SLICE_636.F0 to */SLICE_309.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.238 */SLICE_309.C0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_694.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_694.B0 to */SLICE_694.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_694
ROUTE         1   e 0.908 */SLICE_694.F0 to */SLICE_126.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_560
CTOF_DEL    ---     0.238 */SLICE_126.A0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_686.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_686.B0 to */SLICE_686.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_686
ROUTE         1   e 0.908 */SLICE_686.F0 to */SLICE_121.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_400
CTOF_DEL    ---     0.238 */SLICE_121.A0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_693.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_693.B0 to */SLICE_693.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_693
ROUTE         1   e 0.908 */SLICE_693.F0 to */SLICE_125.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_544
CTOF_DEL    ---     0.238 */SLICE_125.A1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_684.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_684.B0 to */SLICE_684.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_684
ROUTE         1   e 0.908 */SLICE_684.F0 to */SLICE_120.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_368
CTOF_DEL    ---     0.238 */SLICE_120.A0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_616.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_616.B1 to */SLICE_616.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F1 to */SLICE_125.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_82
CTOF_DEL    ---     0.238 */SLICE_125.A0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_542.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_542.A0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_606.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_606.A1 to */SLICE_606.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F1 to */SLICE_311.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.238 */SLICE_311.C0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B1 to */SLICE_151.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_609.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_609.A1 to */SLICE_609.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F1 to */SLICE_307.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.238 */SLICE_307.C1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B1 to */SLICE_152.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_561.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_561.A1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.908 */SLICE_561.F1 to */SLICE_641.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_641.A1 to */SLICE_641.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F1 to */SLICE_161.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a2_0_0
CTOF_DEL    ---     0.238 */SLICE_161.D0 to */SLICE_161.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.908 *u/SLICE_90.Q0 to */SLICE_615.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 */SLICE_615.A1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_608.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_608.B1 to */SLICE_608.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F1 to */SLICE_313.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[13]
CTOF_DEL    ---     0.238 */SLICE_313.C1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_608.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_608.A0 to */SLICE_608.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F0 to */SLICE_313.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.238 */SLICE_313.C0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q0 to */SLICE_619.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_619.A1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_691.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_691.B0 to */SLICE_691.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_691
ROUTE         1   e 0.908 */SLICE_691.F0 to */SLICE_124.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_496
CTOF_DEL    ---     0.238 */SLICE_124.A0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_550.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_550.A0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to */SLICE_670.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_670.B0 to */SLICE_670.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_670
ROUTE         1   e 0.908 */SLICE_670.F0 to */SLICE_526.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr38_3
CTOF_DEL    ---     0.238 */SLICE_526.C0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_605.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_605.B1 to */SLICE_605.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F1 to */SLICE_312.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[11]
CTOF_DEL    ---     0.238 */SLICE_312.C1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_525.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_525.A1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_288.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_288.D0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_605.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_605.A0 to */SLICE_605.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F0 to */SLICE_312.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.238 */SLICE_312.C0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_690.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_690.B0 to */SLICE_690.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_690
ROUTE         1   e 0.908 */SLICE_690.F0 to */SLICE_123.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_464
CTOF_DEL    ---     0.238 */SLICE_123.A0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_548.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_548.A0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_688.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_688.B0 to */SLICE_688.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_688
ROUTE         1   e 0.908 */SLICE_688.F0 to */SLICE_122.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_432
CTOF_DEL    ---     0.238 */SLICE_122.A0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_547.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_547.A0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_546.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_546.A0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_606.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_606.B0 to */SLICE_606.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F0 to */SLICE_310.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.238 */SLICE_310.C1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_545.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_545.A0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_607.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_607.B0 to */SLICE_607.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F0 to */SLICE_310.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[6]
CTOF_DEL    ---     0.238 */SLICE_310.C0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_568.CLK to */SLICE_568.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (from jtaghub16_jtck)
ROUTE         8   e 0.908 */SLICE_568.Q0 to */SLICE_561.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1
CTOF_DEL    ---     0.238 */SLICE_561.C0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_544.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_544.A0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B1 to */SLICE_151.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B0 to */SLICE_151.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_139.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_139.B0 to */SLICE_139.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_716.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_716.B0 to */SLICE_716.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_716
ROUTE         1   e 0.908 */SLICE_716.F0 to */SLICE_138.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_960
CTOF_DEL    ---     0.238 */SLICE_138.A1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_713.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_713.B0 to */SLICE_713.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_713
ROUTE         1   e 0.908 */SLICE_713.F0 to */SLICE_137.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_912
CTOF_DEL    ---     0.238 */SLICE_137.A0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_561.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_561.B1 to */SLICE_561.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE         3   e 0.908 */SLICE_561.F1 to */SLICE_641.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_0_N_8L15_1
CTOF_DEL    ---     0.238 */SLICE_641.A1 to */SLICE_641.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F1 to */SLICE_161.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a2_0_0
CTOF_DEL    ---     0.238 */SLICE_161.D0 to */SLICE_161.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_711.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_711.B0 to */SLICE_711.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_711
ROUTE         1   e 0.908 */SLICE_711.F0 to */SLICE_136.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_880
CTOF_DEL    ---     0.238 */SLICE_136.A0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_714.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_714.B0 to */SLICE_714.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_714
ROUTE         1   e 0.908 */SLICE_714.F0 to */SLICE_137.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_928
CTOF_DEL    ---     0.238 */SLICE_137.A1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_712.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_712.B0 to */SLICE_712.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_712
ROUTE         1   e 0.908 */SLICE_712.F0 to */SLICE_136.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_896
CTOF_DEL    ---     0.238 */SLICE_136.A1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_715.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_715.B0 to */SLICE_715.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_715
ROUTE         1   e 0.908 */SLICE_715.F0 to */SLICE_138.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_944
CTOF_DEL    ---     0.238 */SLICE_138.A0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_710.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_710.B0 to */SLICE_710.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_710
ROUTE         1   e 0.908 */SLICE_710.F0 to */SLICE_135.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_864
CTOF_DEL    ---     0.238 */SLICE_135.A1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_525.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_525.C1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_288.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_288.D0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_709.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_709.B0 to */SLICE_709.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_709
ROUTE         1   e 0.908 */SLICE_709.F0 to */SLICE_134.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_832
CTOF_DEL    ---     0.238 */SLICE_134.A1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_708.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_708.B0 to */SLICE_708.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_708
ROUTE         1   e 0.908 */SLICE_708.F0 to */SLICE_134.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_816
CTOF_DEL    ---     0.238 */SLICE_134.A0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_43.Q1 to */SLICE_618.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 */SLICE_618.A1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_707.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_707.B0 to */SLICE_707.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_707
ROUTE         1   e 0.908 */SLICE_707.F0 to */SLICE_133.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_800
CTOF_DEL    ---     0.238 */SLICE_133.A1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_553.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_553.A0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_678.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_678.B0 to */SLICE_678.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_678
ROUTE         1   e 0.908 */SLICE_678.F0 to */SLICE_133.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_784
CTOF_DEL    ---     0.238 */SLICE_133.A0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_541.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_541.B1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_540.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_540.A0 to */SLICE_540.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 0.908 */SLICE_540.F0 to */SLICE_308.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.238 */SLICE_308.C1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_679.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_679.B0 to */SLICE_679.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_679
ROUTE         1   e 0.908 */SLICE_679.F0 to */SLICE_132.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_768
CTOF_DEL    ---     0.238 */SLICE_132.A1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_609.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_609.B1 to */SLICE_609.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F1 to */SLICE_307.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.238 */SLICE_307.C1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_706.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_706.B0 to */SLICE_706.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_706
ROUTE         1   e 0.908 */SLICE_706.F0 to */SLICE_132.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_752
CTOF_DEL    ---     0.238 */SLICE_132.A0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_629.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_629.B1 to */SLICE_629.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F1 to */SLICE_307.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.238 */SLICE_307.C0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_705.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_705.B0 to */SLICE_705.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_705
ROUTE         1   e 0.908 */SLICE_705.F0 to */SLICE_131.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_736
CTOF_DEL    ---     0.238 */SLICE_131.A1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B1 to */SLICE_152.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_704.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_704.B0 to */SLICE_704.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_704
ROUTE         1   e 0.908 */SLICE_704.F0 to */SLICE_131.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_720
CTOF_DEL    ---     0.238 */SLICE_131.A0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B1 to */SLICE_151.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_703.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_703.B0 to */SLICE_703.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_703
ROUTE         1   e 0.908 */SLICE_703.F0 to */SLICE_130.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_704
CTOF_DEL    ---     0.238 */SLICE_130.A1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q1 to */SLICE_616.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]
CTOF_DEL    ---     0.238 */SLICE_616.D0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_702.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_702.B0 to */SLICE_702.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_702
ROUTE         1   e 0.908 */SLICE_702.F0 to */SLICE_130.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_688
CTOF_DEL    ---     0.238 */SLICE_130.A0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_516.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_516.A1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_701.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_701.B0 to */SLICE_701.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_701
ROUTE         1   e 0.908 */SLICE_701.F0 to */SLICE_129.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_672
CTOF_DEL    ---     0.238 */SLICE_129.A1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_700.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_700.B0 to */SLICE_700.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_700
ROUTE         1   e 0.908 */SLICE_700.F0 to */SLICE_129.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_656
CTOF_DEL    ---     0.238 */SLICE_129.A0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_699.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_699.B0 to */SLICE_699.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_699
ROUTE         1   e 0.908 */SLICE_699.F0 to */SLICE_128.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_640
CTOF_DEL    ---     0.238 */SLICE_128.A1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_698.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_698.B0 to */SLICE_698.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_698
ROUTE         1   e 0.908 */SLICE_698.F0 to */SLICE_128.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_624
CTOF_DEL    ---     0.238 */SLICE_128.A0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_697.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_697.B0 to */SLICE_697.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_697
ROUTE         1   e 0.908 */SLICE_697.F0 to */SLICE_127.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_608
CTOF_DEL    ---     0.238 */SLICE_127.A1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_696.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_696.B0 to */SLICE_696.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_696
ROUTE         1   e 0.908 */SLICE_696.F0 to */SLICE_127.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_592
CTOF_DEL    ---     0.238 */SLICE_127.A0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_695.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_695.B0 to */SLICE_695.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_695
ROUTE         1   e 0.908 */SLICE_695.F0 to */SLICE_126.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_576
CTOF_DEL    ---     0.238 */SLICE_126.A1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B1 to */SLICE_152.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_263.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_263.C0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_258.CLK to */SLICE_258.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_258.Q0 to */SLICE_619.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_619.A0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_515.A1 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_515.A1 to */SLICE_515.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         2   e 0.908 */SLICE_515.F1 to */SLICE_517.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active6
CTOF_DEL    ---     0.238 */SLICE_517.B0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_515.A1 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_515.A1 to */SLICE_515.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         2   e 0.908 */SLICE_515.F1 to */SLICE_517.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active6
CTOF_DEL    ---     0.238 */SLICE_517.B0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_258.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_258.C0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q0 to */SLICE_618.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_618.D1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q1 to */SLICE_618.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_618.B1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_38.Q1 to */SLICE_286.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_286.C1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_35.Q0 to */SLICE_617.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_617.D0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q0 to */SLICE_619.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_619.D1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q1 to */SLICE_617.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 */SLICE_617.B0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q1 to */SLICE_666.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]
CTOF_DEL    ---     0.238 */SLICE_666.B0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_42.Q0 to */SLICE_618.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_618.A0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q1 to */SLICE_274.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_274.C1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_288.Q0 to */SLICE_289.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_289.B1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_617.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_617.B1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.B0 to */SLICE_636.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE         1   e 0.908 */SLICE_636.F0 to */SLICE_309.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.238 */SLICE_309.C0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_688.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_688.B0 to */SLICE_688.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_688
ROUTE         1   e 0.908 */SLICE_688.F0 to */SLICE_122.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_432
CTOF_DEL    ---     0.238 */SLICE_122.A0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_685.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_685.B0 to */SLICE_685.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_685
ROUTE         1   e 0.908 */SLICE_685.F0 to */SLICE_120.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_384
CTOF_DEL    ---     0.238 */SLICE_120.A1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_607.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_607.A1 to */SLICE_607.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F1 to */SLICE_309.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.238 */SLICE_309.C1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_683.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_683.B0 to */SLICE_683.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_683
ROUTE         1   e 0.908 */SLICE_683.F0 to */SLICE_119.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_352
CTOF_DEL    ---     0.238 */SLICE_119.A1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_682.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_682.B0 to */SLICE_682.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_682
ROUTE         1   e 0.908 */SLICE_682.F0 to */SLICE_119.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_336
CTOF_DEL    ---     0.238 */SLICE_119.A0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_541.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_541.C1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_540.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_540.A0 to */SLICE_540.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 0.908 */SLICE_540.F0 to */SLICE_308.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.238 */SLICE_308.C1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q0 to */SLICE_616.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]
CTOF_DEL    ---     0.238 */SLICE_616.A0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B0 to */SLICE_152.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_609.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_609.B0 to */SLICE_609.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F0 to */SLICE_308.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.238 */SLICE_308.C0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_681.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_681.B0 to */SLICE_681.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_681
ROUTE         1   e 0.908 */SLICE_681.F0 to */SLICE_118.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_320
CTOF_DEL    ---     0.238 */SLICE_118.A1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_150.CLK to */SLICE_150.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_150.Q1 to */SLICE_616.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]
CTOF_DEL    ---     0.238 */SLICE_616.B0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B0 to */SLICE_152.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q1 to */SLICE_616.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]
CTOF_DEL    ---     0.238 */SLICE_616.C0 to */SLICE_616.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F0 to */SLICE_556.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_bit_0_3
CTOF_DEL    ---     0.238 */SLICE_556.A1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B1 to */SLICE_152.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_552.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_552.A0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_551.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_551.A0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_691.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_691.B0 to */SLICE_691.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_691
ROUTE         1   e 0.908 */SLICE_691.F0 to */SLICE_124.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_496
CTOF_DEL    ---     0.238 */SLICE_124.A0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_550.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_550.A0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_549.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_549.A0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_690.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_690.B0 to */SLICE_690.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_690
ROUTE         1   e 0.908 */SLICE_690.F0 to */SLICE_123.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_464
CTOF_DEL    ---     0.238 */SLICE_123.A0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_561.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_561.B0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_548.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_548.A0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_547.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_547.A0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_546.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_546.A0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_262.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_262.C0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_545.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_545.A0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_639.CLK to */SLICE_639.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_639.Q0 to */SLICE_561.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1
CTOF_DEL    ---     0.238 */SLICE_561.D0 to */SLICE_561.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_561
ROUTE        15   e 0.908 */SLICE_561.F0 to */SLICE_544.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0s2
CTOF_DEL    ---     0.238 */SLICE_544.A0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_259.CLK to */SLICE_259.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_259.Q0 to */SLICE_274.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_274.A1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_256.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_256.C0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_262.CLK to */SLICE_262.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_262.Q0 to */SLICE_619.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_619.C0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_260.CLK to */SLICE_260.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_260.Q1 to */SLICE_666.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]
CTOF_DEL    ---     0.238 */SLICE_666.C0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_274.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_274.A0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q1 to */SLICE_666.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_666.A0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_694.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_694.B0 to */SLICE_694.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_694
ROUTE         1   e 0.908 */SLICE_694.F0 to */SLICE_126.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_560
CTOF_DEL    ---     0.238 */SLICE_126.A0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q0 to */SLICE_274.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]
CTOF_DEL    ---     0.238 */SLICE_274.D1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_616.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_616.B1 to */SLICE_616.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F1 to */SLICE_125.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_82
CTOF_DEL    ---     0.238 */SLICE_125.A0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q0 to */SLICE_274.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]
CTOF_DEL    ---     0.238 */SLICE_274.B1 to */SLICE_274.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.908 */SLICE_274.F1 to */SLICE_513.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_11
CTOF_DEL    ---     0.238 */SLICE_513.D1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_36.Q0 to */SLICE_618.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 */SLICE_618.D0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_257.CLK to */SLICE_257.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_257.Q0 to */SLICE_619.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]
CTOF_DEL    ---     0.238 */SLICE_619.C1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_261.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_261.C0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q0 to */SLICE_618.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_618.C0 to */SLICE_618.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F0 to */SLICE_523.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_9
CTOF_DEL    ---     0.238 */SLICE_523.B1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_263.CLK to */SLICE_263.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_263.Q1 to */SLICE_619.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]
CTOF_DEL    ---     0.238 */SLICE_619.D0 to */SLICE_619.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F0 to */SLICE_513.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_10
CTOF_DEL    ---     0.238 */SLICE_513.C1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_261.CLK to */SLICE_261.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_261.Q1 to */SLICE_666.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]
CTOF_DEL    ---     0.238 */SLICE_666.D0 to */SLICE_666.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_666
ROUTE         1   e 0.908 */SLICE_666.F0 to */SLICE_513.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_8
CTOF_DEL    ---     0.238 */SLICE_513.A1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_260.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_260.C1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_256.CLK to */SLICE_256.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_256.Q1 to */SLICE_619.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]
CTOF_DEL    ---     0.238 */SLICE_619.B1 to */SLICE_619.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_619
ROUTE         1   e 0.908 */SLICE_619.F1 to */SLICE_513.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17_9
CTOF_DEL    ---     0.238 */SLICE_513.B1 to */SLICE_513.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE        19   e 0.908 */SLICE_513.F1 to */SLICE_257.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active17
CTOF_DEL    ---     0.238 */SLICE_257.C1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_41.Q0 to */SLICE_617.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 */SLICE_617.A0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_288.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_288.A0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_37.Q1 to */SLICE_617.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 */SLICE_617.C0 to */SLICE_617.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F0 to */SLICE_523.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_10
CTOF_DEL    ---     0.238 */SLICE_523.C1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_39.Q1 to */SLICE_286.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 */SLICE_286.A1 to */SLICE_286.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.908 */SLICE_286.F1 to */SLICE_523.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_11
CTOF_DEL    ---     0.238 */SLICE_523.D1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_286.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_286.B0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *1/SLICE_40.Q1 to */SLICE_618.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 */SLICE_618.C1 to */SLICE_618.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_618
ROUTE         1   e 0.908 */SLICE_618.F1 to */SLICE_523.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42_8
CTOF_DEL    ---     0.238 */SLICE_523.A1 to */SLICE_523.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         7   e 0.908 */SLICE_523.F1 to */SLICE_289.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active42
CTOF_DEL    ---     0.238 */SLICE_289.B0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.879ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (3.802ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_629.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_629.A1 to */SLICE_629.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F1 to */SLICE_307.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.238 */SLICE_307.C0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    3.802   (28.3% logic, 71.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_85.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_85.A1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_538.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_538.C0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_85.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_85.A1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_538.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_538.C0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_85.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_85.A1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_538.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_538.C0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_77.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_513.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_513.C0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_520.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_520.B0 to */SLICE_520.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.908 */SLICE_520.F0 to */SLICE_516.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_3_0
CTOF_DEL    ---     0.238 */SLICE_516.B0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_521.B0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_521.B0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F0 to */SLICE_516.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_516.A0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_513.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_513.B0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_520.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_520.A0 to */SLICE_520.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_520
ROUTE         1   e 0.908 */SLICE_520.F0 to */SLICE_516.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wen_3_0
CTOF_DEL    ---     0.238 */SLICE_516.B0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q1 to */SLICE_521.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_521.D0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F0 to */SLICE_516.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_516.A0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_315 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_315.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q0 to */SLICE_521.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_521.C0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F0 to */SLICE_516.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_516.A0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_525.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_525.C1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_524.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_524.C0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_288.Q1 to */SLICE_524.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_524.B1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_527.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_527.B0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.D1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_538.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_538.C0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_554.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_554.C0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_159.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_554.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_554.C0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_157.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_554.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_554.C0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_155.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_554.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_554.C0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_153.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_108.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_513.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_513.D0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_515.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_515.B0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_554.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_554.C0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_158.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_554.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_554.C0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_154.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_72.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_72.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_289.CLK to */SLICE_289.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_289.Q0 to */SLICE_524.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.C1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_525.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_525.A0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_315 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_315.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_288.Q0 to */SLICE_524.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.A1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_527.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_527.B0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_525.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_525.A1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_524.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_524.C0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_551.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_547.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_116.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_117.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_76.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_568.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_628.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_109.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_79.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_78.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_77.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_108.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_602.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_287.CLK to */SLICE_287.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_287.Q0 to */SLICE_521.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_enz
CTOF_DEL    ---     0.238 */SLICE_521.A1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_525.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_525.B0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_288.Q1 to */SLICE_524.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_524.B1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_525.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_525.A0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_289.CLK to */SLICE_289.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_289.Q0 to */SLICE_524.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.C1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_527.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_527.B0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_551.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_547.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_116.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_117.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_76.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_568.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_628.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_109.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_79.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_78.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_538.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_538.B0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_554.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_554.C0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_160.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_554.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_554.C0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_156.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_73.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_73.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.D1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_538.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_538.C0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_288.Q0 to */SLICE_524.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.A1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_525.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_525.A0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_639.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.D1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_538.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_538.C0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_592.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_592.C1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_639.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_592.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_592.A1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.789ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (3.563ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_636.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_636.A1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_602.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    3.563   (23.5% logic, 76.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.673ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.596ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_521.Q0 to */SLICE_521.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_521.A0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.596   (36.6% logic, 63.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.673ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.596ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_521.Q0 to */SLICE_521.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_521.A0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_526.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_526.A0 to */SLICE_526.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_526
ROUTE         3   e 0.908 */SLICE_526.F0 to */SLICE_288.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_288.C1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    3.596   (36.6% logic, 63.4% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.583ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (3.357ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to *u/SLICE_90.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 *u/SLICE_90.A0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.232 *u/SLICE_90.F0 to *u/SLICE_90.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.238 *u/SLICE_90.B1 to *u/SLICE_90.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         1   e 0.232 *u/SLICE_90.F1 to *u/SLICE_90.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59 (to jtaghub16_jtck)
                  --------
                    3.357   (32.1% logic, 67.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.583ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (3.357ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.232 */SLICE_602.Q0 to */SLICE_602.B0 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_602.B0 to */SLICE_602.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602
ROUTE         1   e 0.908 */SLICE_602.F0 to */SLICE_527.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen_2
CTOF_DEL    ---     0.238 */SLICE_527.C1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.357   (32.1% logic, 67.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.583ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (3.357ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_521.Q0 to */SLICE_521.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_521.A0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.232 */SLICE_521.F0 to */SLICE_521.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_521.B1 to */SLICE_521.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F1 to */SLICE_525.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active31
CTOF_DEL    ---     0.238 */SLICE_525.B0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    3.357   (32.1% logic, 67.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.583ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (3.357ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to *u/SLICE_90.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 *u/SLICE_90.A0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.232 *u/SLICE_90.F0 to *u/SLICE_90.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.238 *u/SLICE_90.B1 to *u/SLICE_90.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         1   e 0.232 *u/SLICE_90.F1 to *u/SLICE_90.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59 (to jtaghub16_jtck)
                  --------
                    3.357   (32.1% logic, 67.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.583ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (3.357ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to *u/SLICE_90.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 *u/SLICE_90.A0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.232 *u/SLICE_90.F0 to *u/SLICE_90.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.238 *u/SLICE_90.B1 to *u/SLICE_90.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         1   e 0.232 *u/SLICE_90.F1 to *u/SLICE_90.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59 (to jtaghub16_jtck)
                  --------
                    3.357   (32.1% logic, 67.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.583ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (3.357ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_615.Q0 to */SLICE_615.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_615.C1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    3.357   (32.1% logic, 67.9% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.356ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (3.279ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q1 to *u/SLICE_53.A0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]
C0TOFCO_DE  ---     0.550 *u/SLICE_53.A0 to */SLICE_53.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.001 */SLICE_53.FCO to */SLICE_52.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_52.FCI to *u/SLICE_52.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F1 to */SLICE_195.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.238 */SLICE_195.D0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.279   (44.6% logic, 55.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.286ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (3.209ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q1 to *u/SLICE_53.A0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]
C0TOFCO_DE  ---     0.550 *u/SLICE_53.A0 to */SLICE_53.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.001 */SLICE_53.FCO to */SLICE_52.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_52.FCI to *u/SLICE_52.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F0 to */SLICE_194.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3]
CTOF_DEL    ---     0.238 */SLICE_194.D1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.209   (43.3% logic, 56.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.241ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (3.164ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q0 to *u/SLICE_54.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_54.A1 to */SLICE_54.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_54
ROUTE         1   e 0.001 */SLICE_54.FCO to */SLICE_53.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_53.FCI to */SLICE_53.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.001 */SLICE_53.FCO to */SLICE_52.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_52.FCI to *u/SLICE_52.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F1 to */SLICE_195.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.238 */SLICE_195.D0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.164   (42.5% logic, 57.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_517.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_517.A1 to */SLICE_517.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         1   e 0.232 */SLICE_517.F1 to */SLICE_517.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr7_0
CTOF_DEL    ---     0.238 */SLICE_517.C0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_517.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_517.A1 to */SLICE_517.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         1   e 0.232 */SLICE_517.F1 to */SLICE_517.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr7_0
CTOF_DEL    ---     0.238 */SLICE_517.C0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_166.CLK to */SLICE_166.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_166.Q1 to */SLICE_551.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[5]
CTOF_DEL    ---     0.238 */SLICE_551.A1 to */SLICE_551.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.232 */SLICE_551.F1 to */SLICE_551.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
CTOF_DEL    ---     0.238 */SLICE_551.B0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_166.CLK to */SLICE_166.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_166.Q0 to */SLICE_542.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[4]
CTOF_DEL    ---     0.238 */SLICE_542.A1 to */SLICE_542.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.232 */SLICE_542.F1 to */SLICE_542.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[3]
CTOF_DEL    ---     0.238 */SLICE_542.B0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_160.CLK to */SLICE_160.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_160.Q0 to */SLICE_552.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]
CTOF_DEL    ---     0.238 */SLICE_552.D1 to */SLICE_552.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.232 */SLICE_552.F1 to */SLICE_552.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[13]
CTOF_DEL    ---     0.238 */SLICE_552.B0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_719.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_719.C0 to */SLICE_719.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_719
ROUTE         1   e 0.908 */SLICE_719.F0 to */SLICE_162.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en_3_f0_0_a2_0_0
CTOF_DEL    ---     0.238 */SLICE_162.B1 to */SLICE_162.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.232 */SLICE_162.F1 to */SLICE_162.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.238 */SLICE_162.A0 to */SLICE_162.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_142.CLK to */SLICE_142.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_142.Q0 to */SLICE_481.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]
CTOF_DEL    ---     0.238 */SLICE_481.B1 to */SLICE_481.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.232 */SLICE_481.F1 to */SLICE_481.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1_0
CTOF_DEL    ---     0.238 */SLICE_481.C0 to */SLICE_481.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_481
ROUTE         1   e 0.908 */SLICE_481.F0 to */SLICE_307.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[1]
CTOF_DEL    ---     0.238 */SLICE_307.B1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_551.CLK to */SLICE_551.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_551.Q0 to */SLICE_546.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0
CTOF_DEL    ---     0.238 */SLICE_546.B1 to */SLICE_546.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.232 */SLICE_546.F1 to */SLICE_546.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
CTOF_DEL    ---     0.238 */SLICE_546.B0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.232 */SLICE_556.F1 to */SLICE_556.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_556.B0 to */SLICE_556.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE         1   e 0.908 */SLICE_556.F0 to */SLICE_135.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_848
CTOF_DEL    ---     0.238 */SLICE_135.A0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_551.CLK to */SLICE_551.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_551.Q0 to */SLICE_549.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0
CTOF_DEL    ---     0.238 */SLICE_549.B1 to */SLICE_549.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.232 */SLICE_549.F1 to */SLICE_549.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
CTOF_DEL    ---     0.238 */SLICE_549.B0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_547.CLK to */SLICE_547.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_547.Q0 to */SLICE_549.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0
CTOF_DEL    ---     0.238 */SLICE_549.C1 to */SLICE_549.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.232 */SLICE_549.F1 to */SLICE_549.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
CTOF_DEL    ---     0.238 */SLICE_549.B0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_157.CLK to */SLICE_157.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_157.Q0 to */SLICE_546.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]
CTOF_DEL    ---     0.238 */SLICE_546.D1 to */SLICE_546.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.232 */SLICE_546.F1 to */SLICE_546.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
CTOF_DEL    ---     0.238 */SLICE_546.B0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_289.CLK to */SLICE_289.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_289.Q0 to */SLICE_289.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_289.D1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_617.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_617.B1 to */SLICE_617.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_617
ROUTE         1   e 0.908 */SLICE_617.F1 to */SLICE_288.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17_mb_1[1]
CTOF_DEL    ---     0.238 */SLICE_288.D1 to */SLICE_288.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F1 to *SLICE_288.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_166.CLK to */SLICE_166.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_166.Q1 to */SLICE_548.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[5]
CTOF_DEL    ---     0.238 */SLICE_548.A1 to */SLICE_548.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.232 */SLICE_548.F1 to */SLICE_548.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
CTOF_DEL    ---     0.238 */SLICE_548.B0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.908 */SLICE_541.F1 to */SLICE_314.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_314.A1 to */SLICE_314.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.232 */SLICE_314.F1 to */SLICE_314.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.238 */SLICE_314.C0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_168 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_168.CLK to */SLICE_168.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_168 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_168.Q0 to */SLICE_546.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[8]
CTOF_DEL    ---     0.238 */SLICE_546.A1 to */SLICE_546.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.232 */SLICE_546.F1 to */SLICE_546.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
CTOF_DEL    ---     0.238 */SLICE_546.B0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_547.CLK to */SLICE_547.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_547.Q0 to */SLICE_553.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0
CTOF_DEL    ---     0.238 */SLICE_553.C1 to */SLICE_553.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.232 */SLICE_553.F1 to */SLICE_553.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
CTOF_DEL    ---     0.238 */SLICE_553.B0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_167 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_167.CLK to */SLICE_167.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_167 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_167.Q1 to */SLICE_545.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[7]
CTOF_DEL    ---     0.238 */SLICE_545.A1 to */SLICE_545.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.232 */SLICE_545.F1 to */SLICE_545.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
CTOF_DEL    ---     0.238 */SLICE_545.B0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_547.CLK to */SLICE_547.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_547.Q0 to */SLICE_550.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0
CTOF_DEL    ---     0.238 */SLICE_550.C1 to */SLICE_550.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.232 */SLICE_550.F1 to */SLICE_550.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
CTOF_DEL    ---     0.238 */SLICE_550.B0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_141.CLK to */SLICE_141.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_141.Q1 to */SLICE_478.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]
CTOF_DEL    ---     0.238 */SLICE_478.B1 to */SLICE_478.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.232 */SLICE_478.F1 to */SLICE_478.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_N_2L1
CTOF_DEL    ---     0.238 */SLICE_478.C0 to */SLICE_478.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_478
ROUTE         1   e 0.908 */SLICE_478.F0 to */SLICE_307.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[0]
CTOF_DEL    ---     0.238 */SLICE_307.B0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_551.CLK to */SLICE_551.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_551.Q0 to */SLICE_550.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0
CTOF_DEL    ---     0.238 */SLICE_550.B1 to */SLICE_550.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.232 */SLICE_550.F1 to */SLICE_550.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
CTOF_DEL    ---     0.238 */SLICE_550.B0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_552.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_552.B1 to */SLICE_552.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.232 */SLICE_552.F1 to */SLICE_552.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[13]
CTOF_DEL    ---     0.238 */SLICE_552.B0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_117.Q1 to */SLICE_543.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]
CTOF_DEL    ---     0.238 */SLICE_543.C1 to */SLICE_543.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.232 */SLICE_543.F1 to */SLICE_543.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
CTOF_DEL    ---     0.238 */SLICE_543.B0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_547.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_547.A1 to */SLICE_547.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.232 */SLICE_547.F1 to */SLICE_547.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1_0[8]
CTOF_DEL    ---     0.238 */SLICE_547.B0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_141.CLK to */SLICE_141.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_141.Q0 to */SLICE_566.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]
CTOF_DEL    ---     0.238 */SLICE_566.C0 to */SLICE_566.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         2   e 0.232 */SLICE_566.F0 to */SLICE_566.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/d_N_6_0
CTOF_DEL    ---     0.238 */SLICE_566.A1 to */SLICE_566.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_566
ROUTE         1   e 0.908 */SLICE_566.F1 to */SLICE_141.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7_N_2L1
CTOF_DEL    ---     0.238 */SLICE_141.D0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.232 */SLICE_195.F1 to */SLICE_195.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_195.C0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_158.CLK to */SLICE_158.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_158.Q1 to */SLICE_549.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]
CTOF_DEL    ---     0.238 */SLICE_549.D1 to */SLICE_549.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.232 */SLICE_549.F1 to */SLICE_549.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
CTOF_DEL    ---     0.238 */SLICE_549.B0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_155.CLK to */SLICE_155.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_155.Q0 to */SLICE_542.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]
CTOF_DEL    ---     0.238 */SLICE_542.D1 to */SLICE_542.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.232 */SLICE_542.F1 to */SLICE_542.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[3]
CTOF_DEL    ---     0.238 */SLICE_542.B0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_117.Q1 to */SLICE_544.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]
CTOF_DEL    ---     0.238 */SLICE_544.C1 to */SLICE_544.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.232 */SLICE_544.F1 to */SLICE_544.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
CTOF_DEL    ---     0.238 */SLICE_544.B0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_195.C1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_195.C1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.232 */SLICE_195.F1 to */SLICE_195.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_195.C0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_515.Q0 to */SLICE_515.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_515.B1 to */SLICE_515.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         2   e 0.908 */SLICE_515.F1 to */SLICE_517.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active6
CTOF_DEL    ---     0.238 */SLICE_517.B0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_156.CLK to */SLICE_156.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_156.Q1 to */SLICE_545.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]
CTOF_DEL    ---     0.238 */SLICE_545.D1 to */SLICE_545.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.232 */SLICE_545.F1 to */SLICE_545.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
CTOF_DEL    ---     0.238 */SLICE_545.B0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_525.Q0 to */SLICE_525.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_525.B1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_288.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_288.D0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_615.Q0 to */SLICE_615.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_615.C1 to */SLICE_615.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615
ROUTE         1   e 0.908 */SLICE_615.F1 to */SLICE_516.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/wen_jtck_0_a2_0
CTOF_DEL    ---     0.238 */SLICE_516.D1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_525.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_525.A1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.232 */SLICE_289.F1 to */SLICE_289.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_289.D0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_155.CLK to */SLICE_155.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_155.Q1 to */SLICE_543.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]
CTOF_DEL    ---     0.238 */SLICE_543.D1 to */SLICE_543.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.232 */SLICE_543.F1 to */SLICE_543.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
CTOF_DEL    ---     0.238 */SLICE_543.B0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.232 */SLICE_556.F1 to */SLICE_556.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_556.B0 to */SLICE_556.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE         1   e 0.908 */SLICE_556.F0 to */SLICE_135.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_848
CTOF_DEL    ---     0.238 */SLICE_135.A0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_167 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_167.CLK to */SLICE_167.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_167 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_167.Q0 to */SLICE_550.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[6]
CTOF_DEL    ---     0.238 */SLICE_550.A1 to */SLICE_550.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.232 */SLICE_550.F1 to */SLICE_550.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
CTOF_DEL    ---     0.238 */SLICE_550.B0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_540.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_540.D1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_314.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_314.B1 to */SLICE_314.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.232 */SLICE_314.F1 to */SLICE_314.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.238 */SLICE_314.C0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_166.CLK to */SLICE_166.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_166.Q1 to */SLICE_553.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[5]
CTOF_DEL    ---     0.238 */SLICE_553.A1 to */SLICE_553.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.232 */SLICE_553.F1 to */SLICE_553.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
CTOF_DEL    ---     0.238 */SLICE_553.B0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_160.CLK to */SLICE_160.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_160.Q1 to */SLICE_553.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]
CTOF_DEL    ---     0.238 */SLICE_553.D1 to */SLICE_553.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.232 */SLICE_553.F1 to */SLICE_553.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
CTOF_DEL    ---     0.238 */SLICE_553.B0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_168 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_168.CLK to */SLICE_168.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_168 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_168.Q1 to */SLICE_549.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[11]
CTOF_DEL    ---     0.238 */SLICE_549.A1 to */SLICE_549.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.232 */SLICE_549.F1 to */SLICE_549.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[10]
CTOF_DEL    ---     0.238 */SLICE_549.B0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_547.CLK to */SLICE_547.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_547.Q0 to */SLICE_552.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0
CTOF_DEL    ---     0.238 */SLICE_552.C1 to */SLICE_552.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.232 */SLICE_552.F1 to */SLICE_552.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[13]
CTOF_DEL    ---     0.238 */SLICE_552.B0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_167 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_167.CLK to */SLICE_167.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_167 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_167.Q0 to */SLICE_544.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[6]
CTOF_DEL    ---     0.238 */SLICE_544.A1 to */SLICE_544.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.232 */SLICE_544.F1 to */SLICE_544.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
CTOF_DEL    ---     0.238 */SLICE_544.B0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_159.CLK to */SLICE_159.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_159.Q1 to */SLICE_551.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]
CTOF_DEL    ---     0.238 */SLICE_551.D1 to */SLICE_551.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.232 */SLICE_551.F1 to */SLICE_551.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
CTOF_DEL    ---     0.238 */SLICE_551.B0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_169 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_169.CLK to */SLICE_169.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_169 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_169.Q0 to */SLICE_552.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[14]
CTOF_DEL    ---     0.238 */SLICE_552.A1 to */SLICE_552.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.232 */SLICE_552.F1 to */SLICE_552.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[13]
CTOF_DEL    ---     0.238 */SLICE_552.B0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_159.CLK to */SLICE_159.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_159.Q0 to */SLICE_550.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]
CTOF_DEL    ---     0.238 */SLICE_550.D1 to */SLICE_550.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.232 */SLICE_550.F1 to */SLICE_550.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[11]
CTOF_DEL    ---     0.238 */SLICE_550.B0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_166.CLK to */SLICE_166.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_166 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_166.Q1 to */SLICE_543.A1 Test_reveal_coretop_instance/test_la0_inst_0/rd_dout_tm[5]
CTOF_DEL    ---     0.238 */SLICE_543.A1 to */SLICE_543.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.232 */SLICE_543.F1 to */SLICE_543.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
CTOF_DEL    ---     0.238 */SLICE_543.B0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_117.Q1 to */SLICE_548.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]
CTOF_DEL    ---     0.238 */SLICE_548.C1 to */SLICE_548.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.232 */SLICE_548.F1 to */SLICE_548.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
CTOF_DEL    ---     0.238 */SLICE_548.B0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_551.CLK to */SLICE_551.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_551.Q0 to */SLICE_544.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0
CTOF_DEL    ---     0.238 */SLICE_544.B1 to */SLICE_544.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.232 */SLICE_544.F1 to */SLICE_544.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
CTOF_DEL    ---     0.238 */SLICE_544.B0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_157.CLK to */SLICE_157.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_157.Q1 to */SLICE_547.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]
CTOF_DEL    ---     0.238 */SLICE_547.C1 to */SLICE_547.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.232 */SLICE_547.F1 to */SLICE_547.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1_0[8]
CTOF_DEL    ---     0.238 */SLICE_547.B0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_525.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_525.C1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.232 */SLICE_289.F1 to */SLICE_289.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_289.D0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_117.Q1 to */SLICE_545.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]
CTOF_DEL    ---     0.238 */SLICE_545.C1 to */SLICE_545.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.232 */SLICE_545.F1 to */SLICE_545.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
CTOF_DEL    ---     0.238 */SLICE_545.B0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_540.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_540.B1 to */SLICE_540.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE        16   e 0.908 */SLICE_540.F1 to */SLICE_314.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1053
CTOF_DEL    ---     0.238 */SLICE_314.B1 to */SLICE_314.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.232 */SLICE_314.F1 to */SLICE_314.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.238 */SLICE_314.C0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_156.CLK to */SLICE_156.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_156.Q0 to */SLICE_544.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]
CTOF_DEL    ---     0.238 */SLICE_544.D1 to */SLICE_544.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.232 */SLICE_544.F1 to */SLICE_544.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[5]
CTOF_DEL    ---     0.238 */SLICE_544.B0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_547.CLK to */SLICE_547.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_547.Q0 to */SLICE_551.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0
CTOF_DEL    ---     0.238 */SLICE_551.C1 to */SLICE_551.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.232 */SLICE_551.F1 to */SLICE_551.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
CTOF_DEL    ---     0.238 */SLICE_551.B0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_117.Q0 to */SLICE_542.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]
CTOF_DEL    ---     0.238 */SLICE_542.B1 to */SLICE_542.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.232 */SLICE_542.F1 to */SLICE_542.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[3]
CTOF_DEL    ---     0.238 */SLICE_542.B0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_551.CLK to */SLICE_551.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_551.Q0 to */SLICE_548.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0
CTOF_DEL    ---     0.238 */SLICE_548.B1 to */SLICE_548.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.232 */SLICE_548.F1 to */SLICE_548.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
CTOF_DEL    ---     0.238 */SLICE_548.B0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_117.Q1 to */SLICE_542.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]
CTOF_DEL    ---     0.238 */SLICE_542.C1 to */SLICE_542.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.232 */SLICE_542.F1 to */SLICE_542.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[3]
CTOF_DEL    ---     0.238 */SLICE_542.B0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_551.CLK to */SLICE_551.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_551.Q0 to */SLICE_545.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0
CTOF_DEL    ---     0.238 */SLICE_545.B1 to */SLICE_545.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.232 */SLICE_545.F1 to */SLICE_545.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[6]
CTOF_DEL    ---     0.238 */SLICE_545.B0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_158.CLK to */SLICE_158.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_158.Q0 to */SLICE_548.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]
CTOF_DEL    ---     0.238 */SLICE_548.D1 to */SLICE_548.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.232 */SLICE_548.F1 to */SLICE_548.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[9]
CTOF_DEL    ---     0.238 */SLICE_548.B0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_541.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_541.D1 to */SLICE_541.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE        15   e 0.232 */SLICE_541.F1 to */SLICE_541.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_77
CTOF_DEL    ---     0.238 */SLICE_541.A0 to */SLICE_541.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE         1   e 0.908 */SLICE_541.F0 to */SLICE_311.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.238 */SLICE_311.C1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_515.Q0 to */SLICE_515.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_515.B1 to */SLICE_515.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         2   e 0.908 */SLICE_515.F1 to */SLICE_517.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active6
CTOF_DEL    ---     0.238 */SLICE_517.B0 to */SLICE_517.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_517
ROUTE         2   e 0.908 */SLICE_517.F0 to */SLICE_276.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_1_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_276.D1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_117.Q0 to */SLICE_543.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]
CTOF_DEL    ---     0.238 */SLICE_543.B1 to */SLICE_543.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.232 */SLICE_543.F1 to */SLICE_543.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[4]
CTOF_DEL    ---     0.238 */SLICE_543.B0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_117.CLK to */SLICE_117.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_117.Q1 to */SLICE_546.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]
CTOF_DEL    ---     0.238 */SLICE_546.C1 to */SLICE_546.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.232 */SLICE_546.F1 to */SLICE_546.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[7]
CTOF_DEL    ---     0.238 */SLICE_546.B0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.203ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (3.126ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_553.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_553.B1 to */SLICE_553.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.232 */SLICE_553.F1 to */SLICE_553.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[14]
CTOF_DEL    ---     0.238 */SLICE_553.B0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    3.126   (34.5% logic, 65.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.173ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (3.096ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q0 to *u/SLICE_53.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]
C1TOFCO_DE  ---     0.367 *u/SLICE_53.A1 to */SLICE_53.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.001 */SLICE_53.FCO to */SLICE_52.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_52.FCI to *u/SLICE_52.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F1 to */SLICE_195.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.238 */SLICE_195.D0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    3.096   (41.3% logic, 58.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.173ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (3.096ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q0 to *u/SLICE_54.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_54.A1 to */SLICE_54.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_54
ROUTE         1   e 0.001 */SLICE_54.FCO to */SLICE_53.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0]
FCITOF1_DE  ---     0.310 */SLICE_53.FCI to *u/SLICE_53.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.908 *u/SLICE_53.F1 to */SLICE_194.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2]
CTOF_DEL    ---     0.238 */SLICE_194.D0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    3.096   (41.3% logic, 58.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.173ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.096ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to *u/SLICE_46.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
C1TOFCO_DE  ---     0.367 *u/SLICE_46.A1 to */SLICE_46.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_46
ROUTE         1   e 0.001 */SLICE_46.FCO to */SLICE_45.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_45.FCI to *u/SLICE_45.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_45
ROUTE         1   e 0.908 *u/SLICE_45.F1 to */SLICE_152.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[4]
CTOF_DEL    ---     0.238 */SLICE_152.C0 to */SLICE_152.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    3.096   (41.3% logic, 58.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (3.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q0 to *u/SLICE_54.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_54.A1 to */SLICE_54.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_54
ROUTE         1   e 0.001 */SLICE_54.FCO to */SLICE_53.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_53.FCI to */SLICE_53.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.001 */SLICE_53.FCO to */SLICE_52.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_52.FCI to *u/SLICE_52.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F0 to */SLICE_194.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3]
CTOF_DEL    ---     0.238 */SLICE_194.D1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.094   (41.2% logic, 58.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.171ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.094ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to *u/SLICE_46.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
C1TOFCO_DE  ---     0.367 *u/SLICE_46.A1 to */SLICE_46.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_46
ROUTE         1   e 0.001 */SLICE_46.FCO to */SLICE_45.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_45.FCI to */SLICE_45.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_45
ROUTE         1   e 0.001 */SLICE_45.FCO to */SLICE_44.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_44.FCI to *u/SLICE_44.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_44
ROUTE         1   e 0.908 *u/SLICE_44.F0 to */SLICE_152.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5]
CTOF_DEL    ---     0.238 */SLICE_152.C1 to */SLICE_152.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.094   (41.2% logic, 58.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_525.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_525.C1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.232 */SLICE_525.F1 to */SLICE_525.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_525.D0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_527.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_527.B1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_516.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_516.B1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_527.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_527.A1 to */SLICE_527.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.232 */SLICE_527.F1 to */SLICE_527.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wen
CTOF_DEL    ---     0.238 */SLICE_527.D0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_288.Q0 to */SLICE_524.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.A1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.232 */SLICE_524.F1 to */SLICE_524.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_524.A0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_289.CLK to */SLICE_289.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_289.Q0 to */SLICE_524.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.C1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.232 */SLICE_524.F1 to */SLICE_524.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_524.A0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_48.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_49.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_50.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_51.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_139.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_138.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_137.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_136.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_135.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_134.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_133.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_132.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_131.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_130.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_129.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_128.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_127.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_126.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_125.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_124.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_123.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_122.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_121.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_120.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_119.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_118.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_170 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_170.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_538.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_538.A1 to */SLICE_538.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 0.232 */SLICE_538.F1 to */SLICE_538.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_0_o2_0
CTOF_DEL    ---     0.238 */SLICE_538.D0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_554.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_554.B1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_160.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_554.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_554.B1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_159.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_554.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_554.B1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_158.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_554.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_554.B1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_157.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_554.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_554.B1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_156.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_554.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_554.B1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_155.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_554.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_554.B1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_154.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_554.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_554.B1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_153.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_538.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_538.A1 to */SLICE_538.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 0.232 */SLICE_538.F1 to */SLICE_538.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_0_o2_0
CTOF_DEL    ---     0.238 */SLICE_538.D0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_516.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_516.C1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.232 */SLICE_516.F1 to */SLICE_516.C0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_516.C0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_521.Q0 to */SLICE_521.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_521.A0 to */SLICE_521.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521
ROUTE         2   e 0.908 */SLICE_521.F0 to */SLICE_516.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tt_end[0]
CTOF_DEL    ---     0.238 */SLICE_516.A0 to */SLICE_516.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         1   e 0.908 */SLICE_516.F0 to */SLICE_306.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_525.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_525.A1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.232 */SLICE_525.F1 to */SLICE_525.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_525.D0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_525.Q0 to */SLICE_525.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_525.B1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_524.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_524.C0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_288.Q1 to */SLICE_524.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_524.B1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.232 */SLICE_524.F1 to */SLICE_524.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_524.A0 to */SLICE_524.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         1   e 0.908 */SLICE_524.F0 to */SLICE_289.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_48.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_49.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_50.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_51.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_139.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_138.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_137.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_136.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_135.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_134.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_133.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_132.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_131.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_130.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_129.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_79.Q1 to */SLICE_191.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[15]
CTOF_DEL    ---     0.238 */SLICE_191.A0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_127.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_126.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_125.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_124.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_123.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_122.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_121.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_120.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_119.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_118.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_170 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_170.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_538.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_538.A1 to */SLICE_538.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 0.232 */SLICE_538.F1 to */SLICE_538.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_0_o2_0
CTOF_DEL    ---     0.238 */SLICE_538.D0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_554.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_554.D1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_160.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_554.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_554.D1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_159.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_554.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_554.D1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_158.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_554.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_554.D1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_157.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_554.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_554.D1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_156.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_554.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_554.D1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_155.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_554.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_554.D1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_154.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_554.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_554.D1 to */SLICE_554.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         1   e 0.232 */SLICE_554.F1 to */SLICE_554.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_56
CTOF_DEL    ---     0.238 */SLICE_554.A0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_153.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_79.Q1 to */SLICE_191.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[15]
CTOF_DEL    ---     0.238 */SLICE_191.A0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_79.Q1 to */SLICE_191.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[15]
CTOF_DEL    ---     0.238 */SLICE_191.A0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.232 */SLICE_191.F0 to */SLICE_191.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa
CTOF_DEL    ---     0.238 */SLICE_191.D1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_515.A1 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_515.A1 to */SLICE_515.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         2   e 0.232 */SLICE_515.F1 to */SLICE_515.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active6
CTOF_DEL    ---     0.238 */SLICE_515.A0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.232 */SLICE_514.F1 to */SLICE_514.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_514.A0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.113ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (2.887ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.232 */SLICE_560.F1 to */SLICE_560.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_560.A0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_128.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.887   (29.1% logic, 70.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.103ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (3.026ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q0 to *u/SLICE_53.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]
C1TOFCO_DE  ---     0.367 *u/SLICE_53.A1 to */SLICE_53.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.001 */SLICE_53.FCO to */SLICE_52.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_52.FCI to *u/SLICE_52.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F0 to */SLICE_194.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3]
CTOF_DEL    ---     0.238 */SLICE_194.D1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    3.026   (39.9% logic, 60.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.103ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (3.026ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q0 to *u/SLICE_54.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_54.A1 to */SLICE_54.FCO Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_54
ROUTE         1   e 0.001 */SLICE_54.FCO to */SLICE_53.FCI Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_cry[0]
FCITOF0_DE  ---     0.240 */SLICE_53.FCI to *u/SLICE_53.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.908 *u/SLICE_53.F0 to */SLICE_193.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1]
CTOF_DEL    ---     0.238 */SLICE_193.D1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    3.026   (39.9% logic, 60.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.103ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (3.026ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to *u/SLICE_45.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
C1TOFCO_DE  ---     0.367 *u/SLICE_45.A1 to */SLICE_45.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_45
ROUTE         1   e 0.001 */SLICE_45.FCO to */SLICE_44.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_44.FCI to *u/SLICE_44.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_44
ROUTE         1   e 0.908 *u/SLICE_44.F0 to */SLICE_152.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[5]
CTOF_DEL    ---     0.238 */SLICE_152.C1 to */SLICE_152.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    3.026   (39.9% logic, 60.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    3.103ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (3.026ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to *u/SLICE_46.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
C1TOFCO_DE  ---     0.367 *u/SLICE_46.A1 to */SLICE_46.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_46
ROUTE         1   e 0.001 */SLICE_46.FCO to */SLICE_45.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_45.FCI to *u/SLICE_45.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_45
ROUTE         1   e 0.908 *u/SLICE_45.F0 to */SLICE_151.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_s[3]
CTOF_DEL    ---     0.238 */SLICE_151.C1 to */SLICE_151.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    3.026   (39.9% logic, 60.1% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.894ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (2.817ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_615.CLK to */SLICE_615.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_615.Q0 to */SLICE_726.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat
CTOF_DEL    ---     0.238 */SLICE_726.B0 to */SLICE_726.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_726
ROUTE         1   e 0.908 */SLICE_726.F0 to */SLICE_104.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_6_1
CTOOFX_DEL  ---     0.399 */SLICE_104.C1 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    2.817   (35.5% logic, 64.5% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.862ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (2.785ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q1 to *u/SLICE_52.A0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]
CTOF1_DEL   ---     0.367 *u/SLICE_52.A0 to *u/SLICE_52.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F1 to */SLICE_195.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.238 */SLICE_195.D0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    2.785   (34.8% logic, 65.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.862ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (2.785ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q1 to *u/SLICE_53.A0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]
CTOF1_DEL   ---     0.367 *u/SLICE_53.A0 to *u/SLICE_53.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.908 *u/SLICE_53.F1 to */SLICE_194.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2]
CTOF_DEL    ---     0.238 */SLICE_194.D0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    2.785   (34.8% logic, 65.2% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_85.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_85.A1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_150.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_150.C1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_85.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_85.A1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_150.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_150.C0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_140.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_140.A0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q1 to *u/SLICE_52.A0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]
CTOF_DEL    ---     0.238 *u/SLICE_52.A0 to *u/SLICE_52.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F0 to */SLICE_194.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[3]
CTOF_DEL    ---     0.238 */SLICE_194.D1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_148.CLK to */SLICE_148.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_148.Q0 to */SLICE_552.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]
CTOF_DEL    ---     0.238 */SLICE_552.C0 to */SLICE_552.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_552
ROUTE         1   e 0.908 */SLICE_552.F0 to */SLICE_313.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[13]
CTOF_DEL    ---     0.238 */SLICE_313.B1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_225.CLK to */SLICE_225.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_225.Q0 to */SLICE_688.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[8]
CTOF_DEL    ---     0.238 */SLICE_688.C0 to */SLICE_688.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_688
ROUTE         1   e 0.908 */SLICE_688.F0 to */SLICE_122.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_432
CTOF_DEL    ---     0.238 */SLICE_122.A0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_257.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_257.D1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_223.CLK to */SLICE_223.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_223.Q0 to */SLICE_684.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[4]
CTOF_DEL    ---     0.238 */SLICE_684.C0 to */SLICE_684.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_684
ROUTE         1   e 0.908 */SLICE_684.F0 to */SLICE_120.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_368
CTOF_DEL    ---     0.238 */SLICE_120.A0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_260.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_260.D1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_258.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_258.D0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_259.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_259.D1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_147.CLK to */SLICE_147.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_147.Q1 to */SLICE_551.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]
CTOF_DEL    ---     0.238 */SLICE_551.C0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_258.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_258.D1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_121.CLK to */SLICE_121.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_121.Q0 to */SLICE_685.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]
CTOF_DEL    ---     0.238 */SLICE_685.A0 to */SLICE_685.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_685
ROUTE         1   e 0.908 */SLICE_685.F0 to */SLICE_120.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_384
CTOF_DEL    ---     0.238 */SLICE_120.A1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_262.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_262.D0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_195.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_195.A1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_261.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_261.D0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to *u/SLICE_90.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 *u/SLICE_90.A0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.001 *u/SLICE_90.F0 to */SLICE_90.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_257.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_257.D0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_312.CLK to */SLICE_312.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_312.Q0 to */SLICE_541.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[10]
CTOF_DEL    ---     0.238 */SLICE_541.D0 to */SLICE_541.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE         1   e 0.908 */SLICE_541.F0 to */SLICE_311.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.238 */SLICE_311.C1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_256.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_256.D0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_152.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_152.B0 to */SLICE_152.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_513.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_513.D0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_263.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_263.D1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_513.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_513.C0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_140.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_140.A0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_525.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_525.A1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_286.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_286.C0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_221.CLK to */SLICE_221.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_221.Q1 to */SLICE_681.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[1]
CTOF_DEL    ---     0.238 */SLICE_681.C0 to */SLICE_681.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_681
ROUTE         1   e 0.908 */SLICE_681.F0 to */SLICE_118.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_320
CTOF_DEL    ---     0.238 */SLICE_118.A1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_288.Q1 to */SLICE_524.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_524.B1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_286.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_286.A0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_146.CLK to */SLICE_146.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_146.Q1 to */SLICE_549.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]
CTOF_DEL    ---     0.238 */SLICE_549.C0 to */SLICE_549.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_549
ROUTE         1   e 0.908 */SLICE_549.F0 to */SLICE_312.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[10]
CTOF_DEL    ---     0.238 */SLICE_312.B0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_288.Q0 to */SLICE_524.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.A1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_287.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_287.B0 to */SLICE_287.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_144.CLK to */SLICE_144.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_144.Q1 to */SLICE_545.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]
CTOF_DEL    ---     0.238 */SLICE_545.C0 to */SLICE_545.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_545
ROUTE         1   e 0.908 */SLICE_545.F0 to */SLICE_310.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[6]
CTOF_DEL    ---     0.238 */SLICE_310.B0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_288.Q0 to */SLICE_289.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_289.B1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_288.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_288.D0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_222.CLK to */SLICE_222.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_222.Q0 to */SLICE_682.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[2]
CTOF_DEL    ---     0.238 */SLICE_682.C0 to */SLICE_682.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_682
ROUTE         1   e 0.908 */SLICE_682.F0 to */SLICE_119.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_336
CTOF_DEL    ---     0.238 */SLICE_119.A0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_288.Q0 to */SLICE_524.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.A1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_289.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_289.A0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_105.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_105.A0 to */SLICE_105.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105
ROUTE         1   e 0.001 */SLICE_105.F0 to *SLICE_105.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_29_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_195.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_195.A1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_105.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_105.A0 to */SLICE_105.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105
ROUTE         1   e 0.001 */SLICE_105.F0 to *SLICE_105.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_29_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_274.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_274.B0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_139.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_139.B0 to */SLICE_139.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_126.CLK to */SLICE_126.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_126.Q0 to */SLICE_693.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]
CTOF_DEL    ---     0.238 */SLICE_693.A0 to */SLICE_693.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_693
ROUTE         1   e 0.908 */SLICE_693.F0 to */SLICE_125.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_544
CTOF_DEL    ---     0.238 */SLICE_125.A1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_139.CLK to */SLICE_139.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_139.Q0 to */SLICE_716.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]
CTOF_DEL    ---     0.238 */SLICE_716.A0 to */SLICE_716.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_716
ROUTE         1   e 0.908 */SLICE_716.F0 to */SLICE_138.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_960
CTOF_DEL    ---     0.238 */SLICE_138.A1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_313.CLK to */SLICE_313.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_313.Q0 to */SLICE_605.D1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[12]
CTOF_DEL    ---     0.238 */SLICE_605.D1 to */SLICE_605.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F1 to */SLICE_312.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[11]
CTOF_DEL    ---     0.238 */SLICE_312.C1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_137.CLK to */SLICE_137.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_137.Q1 to */SLICE_713.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]
CTOF_DEL    ---     0.238 */SLICE_713.A0 to */SLICE_713.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_713
ROUTE         1   e 0.908 */SLICE_713.F0 to */SLICE_137.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_912
CTOF_DEL    ---     0.238 */SLICE_137.A0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_310.CLK to */SLICE_310.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_310.Q0 to */SLICE_607.D1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[6]
CTOF_DEL    ---     0.238 */SLICE_607.D1 to */SLICE_607.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F1 to */SLICE_309.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.238 */SLICE_309.C1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_136.CLK to */SLICE_136.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_136.Q1 to */SLICE_711.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]
CTOF_DEL    ---     0.238 */SLICE_711.A0 to */SLICE_711.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_711
ROUTE         1   e 0.908 */SLICE_711.F0 to */SLICE_136.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_880
CTOF_DEL    ---     0.238 */SLICE_136.A0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_602.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_602.D1 to */SLICE_602.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602
ROUTE         1   e 0.908 */SLICE_602.F1 to */SLICE_140.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4
CTOF_DEL    ---     0.238 */SLICE_140.D0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_138.CLK to */SLICE_138.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_138.Q0 to */SLICE_714.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]
CTOF_DEL    ---     0.238 */SLICE_714.A0 to */SLICE_714.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_714
ROUTE         1   e 0.908 */SLICE_714.F0 to */SLICE_137.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_928
CTOF_DEL    ---     0.238 */SLICE_137.A1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_723.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_723.B0 to */SLICE_723.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_723
ROUTE         2   e 0.908 */SLICE_723.F0 to */SLICE_153.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc19
CTOF_DEL    ---     0.238 */SLICE_153.A0 to */SLICE_153.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_137.CLK to */SLICE_137.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_137.Q0 to */SLICE_712.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]
CTOF_DEL    ---     0.238 */SLICE_712.A0 to */SLICE_712.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_712
ROUTE         1   e 0.908 */SLICE_712.F0 to */SLICE_136.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_896
CTOF_DEL    ---     0.238 */SLICE_136.A1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_193.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_193.A1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_135.CLK to */SLICE_135.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_135.Q1 to */SLICE_556.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]
CTOF_DEL    ---     0.238 */SLICE_556.A0 to */SLICE_556.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE         1   e 0.908 */SLICE_556.F0 to */SLICE_135.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_848
CTOF_DEL    ---     0.238 */SLICE_135.A0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_260.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_260.D0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_138.CLK to */SLICE_138.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_138.Q1 to */SLICE_715.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]
CTOF_DEL    ---     0.238 */SLICE_715.A0 to */SLICE_715.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_715
ROUTE         1   e 0.908 */SLICE_715.F0 to */SLICE_138.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_944
CTOF_DEL    ---     0.238 */SLICE_138.A0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_228.CLK to */SLICE_228.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_228.Q0 to */SLICE_616.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[14]
CTOF_DEL    ---     0.238 */SLICE_616.C1 to */SLICE_616.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F1 to */SLICE_125.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_82
CTOF_DEL    ---     0.238 */SLICE_125.A0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_136.CLK to */SLICE_136.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_136.Q0 to */SLICE_710.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]
CTOF_DEL    ---     0.238 */SLICE_710.A0 to */SLICE_710.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_710
ROUTE         1   e 0.908 */SLICE_710.F0 to */SLICE_135.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_864
CTOF_DEL    ---     0.238 */SLICE_135.A1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay mg5ahub/SLICE_327 to mg5ahub/SLICE_326 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_327.CLK to */SLICE_327.Q0 mg5ahub/SLICE_327 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_327.Q0 to */SLICE_621.D1 mg5ahub/bit_count_3
CTOF_DEL    ---     0.238 */SLICE_621.D1 to */SLICE_621.F1 mg5ahub/SLICE_621
ROUTE         1   e 0.908 */SLICE_621.F1 to */SLICE_326.C1 mg5ahub/un8_bit_count_p4
CTOF_DEL    ---     0.238 */SLICE_326.C1 to */SLICE_326.F1 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F1 to *SLICE_326.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_135.CLK to */SLICE_135.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_135.Q0 to */SLICE_709.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]
CTOF_DEL    ---     0.238 */SLICE_709.A0 to */SLICE_709.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_709
ROUTE         1   e 0.908 */SLICE_709.F0 to */SLICE_134.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_832
CTOF_DEL    ---     0.238 */SLICE_134.A1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_144.CLK to */SLICE_144.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_144.Q0 to */SLICE_544.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]
CTOF_DEL    ---     0.238 */SLICE_544.C0 to */SLICE_544.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_544
ROUTE         1   e 0.908 */SLICE_544.F0 to */SLICE_309.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[5]
CTOF_DEL    ---     0.238 */SLICE_309.B1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_134.CLK to */SLICE_134.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_134.Q1 to */SLICE_708.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]
CTOF_DEL    ---     0.238 */SLICE_708.A0 to */SLICE_708.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_708
ROUTE         1   e 0.908 */SLICE_708.F0 to */SLICE_134.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_816
CTOF_DEL    ---     0.238 */SLICE_134.A0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_148.CLK to */SLICE_148.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_148.Q1 to */SLICE_553.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]
CTOF_DEL    ---     0.238 */SLICE_553.C0 to */SLICE_553.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_553
ROUTE         1   e 0.908 */SLICE_553.F0 to */SLICE_314.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[14]
CTOF_DEL    ---     0.238 */SLICE_314.B0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_134.CLK to */SLICE_134.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_134.Q0 to */SLICE_707.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]
CTOF_DEL    ---     0.238 */SLICE_707.A0 to */SLICE_707.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_707
ROUTE         1   e 0.908 */SLICE_707.F0 to */SLICE_133.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_800
CTOF_DEL    ---     0.238 */SLICE_133.A1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_124.CLK to */SLICE_124.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_124.Q0 to */SLICE_717.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]
CTOF_DEL    ---     0.238 */SLICE_717.A0 to */SLICE_717.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_717
ROUTE         1   e 0.908 */SLICE_717.F0 to */SLICE_123.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_84
CTOF_DEL    ---     0.238 */SLICE_123.A1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_133.CLK to */SLICE_133.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_133.Q1 to */SLICE_678.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]
CTOF_DEL    ---     0.238 */SLICE_678.A0 to */SLICE_678.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_678
ROUTE         1   e 0.908 */SLICE_678.F0 to */SLICE_133.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_784
CTOF_DEL    ---     0.238 */SLICE_133.A0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_123.CLK to */SLICE_123.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_123.Q0 to */SLICE_689.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]
CTOF_DEL    ---     0.238 */SLICE_689.A0 to */SLICE_689.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_689
ROUTE         1   e 0.908 */SLICE_689.F0 to */SLICE_122.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_448
CTOF_DEL    ---     0.238 */SLICE_122.A1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_133.CLK to */SLICE_133.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_133.Q0 to */SLICE_679.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]
CTOF_DEL    ---     0.238 */SLICE_679.A0 to */SLICE_679.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_679
ROUTE         1   e 0.908 */SLICE_679.F0 to */SLICE_132.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_768
CTOF_DEL    ---     0.238 */SLICE_132.A1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_310.CLK to */SLICE_310.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_310.Q1 to */SLICE_606.C0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[7]
CTOF_DEL    ---     0.238 */SLICE_606.C0 to */SLICE_606.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F0 to */SLICE_310.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.238 */SLICE_310.C1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_132.CLK to */SLICE_132.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_132.Q1 to */SLICE_706.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]
CTOF_DEL    ---     0.238 */SLICE_706.A0 to */SLICE_706.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_706
ROUTE         1   e 0.908 */SLICE_706.F0 to */SLICE_132.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_752
CTOF_DEL    ---     0.238 */SLICE_132.A0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_143.CLK to */SLICE_143.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_143.Q1 to */SLICE_543.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]
CTOF_DEL    ---     0.238 */SLICE_543.C0 to */SLICE_543.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_543
ROUTE         1   e 0.908 */SLICE_543.F0 to */SLICE_309.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[4]
CTOF_DEL    ---     0.238 */SLICE_309.B0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_131.CLK to */SLICE_131.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_131.Q1 to */SLICE_704.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]
CTOF_DEL    ---     0.238 */SLICE_704.A0 to */SLICE_704.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_704
ROUTE         1   e 0.908 */SLICE_704.F0 to */SLICE_131.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_720
CTOF_DEL    ---     0.238 */SLICE_131.A0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_120.CLK to */SLICE_120.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_120.Q0 to */SLICE_683.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]
CTOF_DEL    ---     0.238 */SLICE_683.A0 to */SLICE_683.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_683
ROUTE         1   e 0.908 */SLICE_683.F0 to */SLICE_119.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_352
CTOF_DEL    ---     0.238 */SLICE_119.A1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_131.CLK to */SLICE_131.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_131.Q0 to */SLICE_703.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]
CTOF_DEL    ---     0.238 */SLICE_703.A0 to */SLICE_703.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_703
ROUTE         1   e 0.908 */SLICE_703.F0 to */SLICE_130.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_704
CTOF_DEL    ---     0.238 */SLICE_130.A1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_307.CLK to */SLICE_307.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (from jtaghub16_jtck)
ROUTE        12   e 0.908 */SLICE_307.Q1 to */SLICE_629.D1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[1]
CTOF_DEL    ---     0.238 */SLICE_629.D1 to */SLICE_629.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F1 to */SLICE_307.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.238 */SLICE_307.C0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_130.CLK to */SLICE_130.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_130.Q1 to */SLICE_702.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]
CTOF_DEL    ---     0.238 */SLICE_702.A0 to */SLICE_702.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_702
ROUTE         1   e 0.908 */SLICE_702.F0 to */SLICE_130.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_688
CTOF_DEL    ---     0.238 */SLICE_130.A0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B1 to */SLICE_151.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_130.CLK to */SLICE_130.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_130.Q0 to */SLICE_701.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]
CTOF_DEL    ---     0.238 */SLICE_701.A0 to */SLICE_701.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_701
ROUTE         1   e 0.908 */SLICE_701.F0 to */SLICE_129.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_672
CTOF_DEL    ---     0.238 */SLICE_129.A1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_516.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_516.B1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_129.CLK to */SLICE_129.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_129.Q1 to */SLICE_700.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]
CTOF_DEL    ---     0.238 */SLICE_700.A0 to */SLICE_700.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_700
ROUTE         1   e 0.908 */SLICE_700.F0 to */SLICE_129.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_656
CTOF_DEL    ---     0.238 */SLICE_129.A0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_194.A0 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_194.A0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to *u/SLICE_75.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 *u/SLICE_75.A0 to *u/SLICE_75.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75
ROUTE         1   e 0.001 *u/SLICE_75.F0 to */SLICE_75.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_43_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_261.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_261.D1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_129.CLK to */SLICE_129.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_129.Q0 to */SLICE_699.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]
CTOF_DEL    ---     0.238 */SLICE_699.A0 to */SLICE_699.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_699
ROUTE         1   e 0.908 */SLICE_699.F0 to */SLICE_128.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_640
CTOF_DEL    ---     0.238 */SLICE_128.A1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_256.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_256.D1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_128.CLK to */SLICE_128.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_128.Q1 to */SLICE_698.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]
CTOF_DEL    ---     0.238 */SLICE_698.A0 to */SLICE_698.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_698
ROUTE         1   e 0.908 */SLICE_698.F0 to */SLICE_128.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_624
CTOF_DEL    ---     0.238 */SLICE_128.A0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_288.Q0 to */SLICE_524.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.A1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_286.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_286.A0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_128.CLK to */SLICE_128.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_128.Q0 to */SLICE_697.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]
CTOF_DEL    ---     0.238 */SLICE_697.A0 to */SLICE_697.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_697
ROUTE         1   e 0.908 */SLICE_697.F0 to */SLICE_127.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_608
CTOF_DEL    ---     0.238 */SLICE_127.A1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_560.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_560.A1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_111.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_111.A0 to */SLICE_111.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE         1   e 0.001 */SLICE_111.F0 to *SLICE_111.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_45_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_127.CLK to */SLICE_127.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_127.Q1 to */SLICE_696.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]
CTOF_DEL    ---     0.238 */SLICE_696.A0 to */SLICE_696.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_696
ROUTE         1   e 0.908 */SLICE_696.F0 to */SLICE_127.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_592
CTOF_DEL    ---     0.238 */SLICE_127.A0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_227.CLK to */SLICE_227.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_227.Q1 to */SLICE_692.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[13]
CTOF_DEL    ---     0.238 */SLICE_692.C0 to */SLICE_692.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_692
ROUTE         1   e 0.908 */SLICE_692.F0 to */SLICE_124.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_512
CTOF_DEL    ---     0.238 */SLICE_124.A1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_127.CLK to */SLICE_127.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_127.Q0 to */SLICE_695.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]
CTOF_DEL    ---     0.238 */SLICE_695.A0 to */SLICE_695.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_695
ROUTE         1   e 0.908 */SLICE_695.F0 to */SLICE_126.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_576
CTOF_DEL    ---     0.238 */SLICE_126.A1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_227.CLK to */SLICE_227.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_227.Q0 to */SLICE_691.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[12]
CTOF_DEL    ---     0.238 */SLICE_691.C0 to */SLICE_691.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_691
ROUTE         1   e 0.908 */SLICE_691.F0 to */SLICE_124.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_496
CTOF_DEL    ---     0.238 */SLICE_124.A0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_263.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_263.D1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_226.CLK to */SLICE_226.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_226.Q0 to */SLICE_690.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[10]
CTOF_DEL    ---     0.238 */SLICE_690.C0 to */SLICE_690.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_690
ROUTE         1   e 0.908 */SLICE_690.F0 to */SLICE_123.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_464
CTOF_DEL    ---     0.238 */SLICE_123.A0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_262.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_262.D1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_311.CLK to */SLICE_311.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_311.Q0 to */SLICE_606.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[8]
CTOF_DEL    ---     0.238 */SLICE_606.D0 to */SLICE_606.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F0 to */SLICE_310.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[7]
CTOF_DEL    ---     0.238 */SLICE_310.C1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_274.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_274.B0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_224.CLK to */SLICE_224.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_224.Q0 to */SLICE_686.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[6]
CTOF_DEL    ---     0.238 */SLICE_686.C0 to */SLICE_686.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_686
ROUTE         1   e 0.908 */SLICE_686.F0 to */SLICE_121.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_400
CTOF_DEL    ---     0.238 */SLICE_121.A0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_513.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_513.C0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_309.CLK to */SLICE_309.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_309.Q0 to */SLICE_540.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[4]
CTOF_DEL    ---     0.238 */SLICE_540.D0 to */SLICE_540.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 0.908 */SLICE_540.F0 to */SLICE_308.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.238 */SLICE_308.C1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_513.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_513.D0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_140.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_140.A0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_513.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_513.B0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B1 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_525.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_525.C1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_286.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_286.C0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_516.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]
CTOF_DEL    ---     0.238 */SLICE_516.C1 to */SLICE_516.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516
ROUTE         3   e 0.908 */SLICE_516.F1 to */SLICE_191.B0 Test_reveal_coretop_instance/test_la0_inst_0/wen_jtck
CTOF_DEL    ---     0.238 */SLICE_191.B0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_289.CLK to */SLICE_289.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_289.Q0 to */SLICE_524.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.C1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_286.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_286.A0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q0 to *u/SLICE_53.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]
CTOF_DEL    ---     0.238 *u/SLICE_53.A1 to *u/SLICE_53.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.908 *u/SLICE_53.F1 to */SLICE_194.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[2]
CTOF_DEL    ---     0.238 */SLICE_194.D0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_289.CLK to */SLICE_289.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_289.Q0 to */SLICE_524.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.C1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_287.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_287.B0 to */SLICE_287.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay mg5ahub/SLICE_326 to mg5ahub/SLICE_326 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_326.CLK to */SLICE_326.Q0 mg5ahub/SLICE_326 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_326.Q0 to */SLICE_621.C1 mg5ahub/bit_count_2
CTOF_DEL    ---     0.238 */SLICE_621.C1 to */SLICE_621.F1 mg5ahub/SLICE_621
ROUTE         1   e 0.908 */SLICE_621.F1 to */SLICE_326.C1 mg5ahub/un8_bit_count_p4
CTOF_DEL    ---     0.238 */SLICE_326.C1 to */SLICE_326.F1 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F1 to *SLICE_326.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_288.Q1 to */SLICE_524.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_524.B1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_287.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_287.B0 to */SLICE_287.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_262.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_262.D1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_288.Q1 to */SLICE_289.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_289.C1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_288.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_288.D0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_259.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_259.D0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_289.CLK to */SLICE_289.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_289.Q0 to */SLICE_524.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_524.C1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_289.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_289.A0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_274.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_274.B0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to *u/SLICE_90.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 *u/SLICE_90.A0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.001 *u/SLICE_90.F0 to */SLICE_90.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_308.CLK to */SLICE_308.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_308.Q1 to */SLICE_609.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[3]
CTOF_DEL    ---     0.238 */SLICE_609.D0 to */SLICE_609.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F0 to */SLICE_308.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.238 */SLICE_308.C0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to *u/SLICE_90.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 *u/SLICE_90.A0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.001 *u/SLICE_90.F0 to */SLICE_90.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_641.D1 Test_reveal_coretop_instance/test_la0_inst_0/addr[13]
CTOF_DEL    ---     0.238 */SLICE_641.D1 to */SLICE_641.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F1 to */SLICE_161.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a2_0_0
CTOF_DEL    ---     0.238 */SLICE_161.D0 to */SLICE_161.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_105.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_105.B0 to */SLICE_105.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105
ROUTE         1   e 0.001 */SLICE_105.F0 to *SLICE_105.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_29_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_105.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_105.B0 to */SLICE_105.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105
ROUTE         1   e 0.001 */SLICE_105.F0 to *SLICE_105.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_29_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_147.CLK to */SLICE_147.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_147.Q0 to */SLICE_550.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]
CTOF_DEL    ---     0.238 */SLICE_550.C0 to */SLICE_550.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_550
ROUTE         1   e 0.908 */SLICE_550.F0 to */SLICE_312.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[11]
CTOF_DEL    ---     0.238 */SLICE_312.B1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to */SLICE_111.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 */SLICE_111.A0 to */SLICE_111.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE         1   e 0.001 */SLICE_111.F0 to *SLICE_111.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_45_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_308.CLK to */SLICE_308.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_308.Q0 to */SLICE_609.D1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[2]
CTOF_DEL    ---     0.238 */SLICE_609.D1 to */SLICE_609.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F1 to */SLICE_307.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.238 */SLICE_307.C1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_139.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_139.B0 to */SLICE_139.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_307.CLK to */SLICE_307.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (from jtaghub16_jtck)
ROUTE        28   e 0.908 */SLICE_307.Q0 to */SLICE_629.C1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[0]
CTOF_DEL    ---     0.238 */SLICE_629.C1 to */SLICE_629.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_629
ROUTE         1   e 0.908 */SLICE_629.F1 to */SLICE_307.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[0]
CTOF_DEL    ---     0.238 */SLICE_307.C0 to */SLICE_307.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F0 to *SLICE_307.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_241.CLK to */SLICE_241.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_241.Q1 to */SLICE_716.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[41]
CTOF_DEL    ---     0.238 */SLICE_716.C0 to */SLICE_716.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_716
ROUTE         1   e 0.908 */SLICE_716.F0 to */SLICE_138.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_960
CTOF_DEL    ---     0.238 */SLICE_138.A1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_125.CLK to */SLICE_125.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_125.Q0 to */SLICE_692.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]
CTOF_DEL    ---     0.238 */SLICE_692.A0 to */SLICE_692.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_692
ROUTE         1   e 0.908 */SLICE_692.F0 to */SLICE_124.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_512
CTOF_DEL    ---     0.238 */SLICE_124.A1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_240.CLK to */SLICE_240.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_240.Q0 to */SLICE_713.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[38]
CTOF_DEL    ---     0.238 */SLICE_713.C0 to */SLICE_713.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_713
ROUTE         1   e 0.908 */SLICE_713.F0 to */SLICE_137.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_912
CTOF_DEL    ---     0.238 */SLICE_137.A0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_124.CLK to */SLICE_124.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_124.Q1 to */SLICE_691.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]
CTOF_DEL    ---     0.238 */SLICE_691.A0 to */SLICE_691.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_691
ROUTE         1   e 0.908 */SLICE_691.F0 to */SLICE_124.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_496
CTOF_DEL    ---     0.238 */SLICE_124.A0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_239.CLK to */SLICE_239.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_239.Q0 to */SLICE_711.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[36]
CTOF_DEL    ---     0.238 */SLICE_711.C0 to */SLICE_711.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_711
ROUTE         1   e 0.908 */SLICE_711.F0 to */SLICE_136.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_880
CTOF_DEL    ---     0.238 */SLICE_136.A0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_312.CLK to */SLICE_312.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_312.Q1 to */SLICE_605.C1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[11]
CTOF_DEL    ---     0.238 */SLICE_605.C1 to */SLICE_605.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F1 to */SLICE_312.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[11]
CTOF_DEL    ---     0.238 */SLICE_312.C1 to */SLICE_312.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F1 to *SLICE_312.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_240.CLK to */SLICE_240.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_240.Q1 to */SLICE_714.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[39]
CTOF_DEL    ---     0.238 */SLICE_714.C0 to */SLICE_714.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_714
ROUTE         1   e 0.908 */SLICE_714.F0 to */SLICE_137.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_928
CTOF_DEL    ---     0.238 */SLICE_137.A1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_123.CLK to */SLICE_123.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_123.Q1 to */SLICE_690.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]
CTOF_DEL    ---     0.238 */SLICE_690.A0 to */SLICE_690.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_690
ROUTE         1   e 0.908 */SLICE_690.F0 to */SLICE_123.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_464
CTOF_DEL    ---     0.238 */SLICE_123.A0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_239.CLK to */SLICE_239.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_239.Q1 to */SLICE_712.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[37]
CTOF_DEL    ---     0.238 */SLICE_712.C0 to */SLICE_712.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_712
ROUTE         1   e 0.908 */SLICE_712.F0 to */SLICE_136.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_896
CTOF_DEL    ---     0.238 */SLICE_136.A1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_311.CLK to */SLICE_311.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_311.Q1 to */SLICE_541.C0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[9]
CTOF_DEL    ---     0.238 */SLICE_541.C0 to */SLICE_541.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_541
ROUTE         1   e 0.908 */SLICE_541.F0 to */SLICE_311.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[9]
CTOF_DEL    ---     0.238 */SLICE_311.C1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_238.CLK to */SLICE_238.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_238.Q0 to */SLICE_556.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[34]
CTOF_DEL    ---     0.238 */SLICE_556.C0 to */SLICE_556.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE         1   e 0.908 */SLICE_556.F0 to */SLICE_135.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_848
CTOF_DEL    ---     0.238 */SLICE_135.A0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_145.CLK to */SLICE_145.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_145.Q1 to */SLICE_547.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]
CTOF_DEL    ---     0.238 */SLICE_547.C0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_241.CLK to */SLICE_241.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_241.Q0 to */SLICE_715.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[40]
CTOF_DEL    ---     0.238 */SLICE_715.C0 to */SLICE_715.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_715
ROUTE         1   e 0.908 */SLICE_715.F0 to */SLICE_138.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_944
CTOF_DEL    ---     0.238 */SLICE_138.A0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_224.CLK to */SLICE_224.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_224.Q1 to */SLICE_687.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[7]
CTOF_DEL    ---     0.238 */SLICE_687.C0 to */SLICE_687.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_687
ROUTE         1   e 0.908 */SLICE_687.F0 to */SLICE_121.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_416
CTOF_DEL    ---     0.238 */SLICE_121.A1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_238.CLK to */SLICE_238.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_238.Q1 to */SLICE_710.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[35]
CTOF_DEL    ---     0.238 */SLICE_710.C0 to */SLICE_710.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_710
ROUTE         1   e 0.908 */SLICE_710.F0 to */SLICE_135.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_864
CTOF_DEL    ---     0.238 */SLICE_135.A1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_309.CLK to */SLICE_309.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_309.Q1 to */SLICE_607.C1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[5]
CTOF_DEL    ---     0.238 */SLICE_607.C1 to */SLICE_607.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F1 to */SLICE_309.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[5]
CTOF_DEL    ---     0.238 */SLICE_309.C1 to */SLICE_309.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F1 to *SLICE_309.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_237.CLK to */SLICE_237.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_237.Q1 to */SLICE_709.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[33]
CTOF_DEL    ---     0.238 */SLICE_709.C0 to */SLICE_709.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_709
ROUTE         1   e 0.908 */SLICE_709.F0 to */SLICE_134.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_832
CTOF_DEL    ---     0.238 */SLICE_134.A1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_121.CLK to */SLICE_121.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_121.Q1 to */SLICE_686.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]
CTOF_DEL    ---     0.238 */SLICE_686.A0 to */SLICE_686.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_686
ROUTE         1   e 0.908 */SLICE_686.F0 to */SLICE_121.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_400
CTOF_DEL    ---     0.238 */SLICE_121.A0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_237.CLK to */SLICE_237.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_237.Q0 to */SLICE_708.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[32]
CTOF_DEL    ---     0.238 */SLICE_708.C0 to */SLICE_708.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_708
ROUTE         1   e 0.908 */SLICE_708.F0 to */SLICE_134.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_816
CTOF_DEL    ---     0.238 */SLICE_134.A0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_120.CLK to */SLICE_120.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_120.Q1 to */SLICE_684.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]
CTOF_DEL    ---     0.238 */SLICE_684.A0 to */SLICE_684.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_684
ROUTE         1   e 0.908 */SLICE_684.F0 to */SLICE_120.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_368
CTOF_DEL    ---     0.238 */SLICE_120.A0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_236.CLK to */SLICE_236.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_236.Q1 to */SLICE_707.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[31]
CTOF_DEL    ---     0.238 */SLICE_707.C0 to */SLICE_707.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_707
ROUTE         1   e 0.908 */SLICE_707.F0 to */SLICE_133.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_800
CTOF_DEL    ---     0.238 */SLICE_133.A1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_308.CLK to */SLICE_308.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_308.Q1 to */SLICE_540.C0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[3]
CTOF_DEL    ---     0.238 */SLICE_540.C0 to */SLICE_540.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_540
ROUTE         1   e 0.908 */SLICE_540.F0 to */SLICE_308.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[3]
CTOF_DEL    ---     0.238 */SLICE_308.C1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_236.CLK to */SLICE_236.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_236.Q0 to */SLICE_678.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[30]
CTOF_DEL    ---     0.238 */SLICE_678.C0 to */SLICE_678.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_678
ROUTE         1   e 0.908 */SLICE_678.F0 to */SLICE_133.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_784
CTOF_DEL    ---     0.238 */SLICE_133.A0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_308.CLK to */SLICE_308.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (from jtaghub16_jtck)
ROUTE         9   e 0.908 */SLICE_308.Q0 to */SLICE_609.C0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[2]
CTOF_DEL    ---     0.238 */SLICE_609.C0 to */SLICE_609.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F0 to */SLICE_308.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[2]
CTOF_DEL    ---     0.238 */SLICE_308.C0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_235.CLK to */SLICE_235.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_235.Q1 to */SLICE_679.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[29]
CTOF_DEL    ---     0.238 */SLICE_679.C0 to */SLICE_679.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_679
ROUTE         1   e 0.908 */SLICE_679.F0 to */SLICE_132.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_768
CTOF_DEL    ---     0.238 */SLICE_132.A1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_118.CLK to */SLICE_118.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_118.Q1 to */SLICE_680.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]
CTOF_DEL    ---     0.238 */SLICE_680.A0 to */SLICE_680.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_680
ROUTE         1   e 0.908 */SLICE_680.F0 to */SLICE_118.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_304
CTOF_DEL    ---     0.238 */SLICE_118.A0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_235.CLK to */SLICE_235.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_235.Q0 to */SLICE_706.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[28]
CTOF_DEL    ---     0.238 */SLICE_706.C0 to */SLICE_706.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_706
ROUTE         1   e 0.908 */SLICE_706.F0 to */SLICE_132.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_752
CTOF_DEL    ---     0.238 */SLICE_132.A0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_143.CLK to */SLICE_143.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_143.Q0 to */SLICE_725.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]
CTOF_DEL    ---     0.238 */SLICE_725.A0 to */SLICE_725.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_725
ROUTE         1   e 0.908 */SLICE_725.F0 to */SLICE_141.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_2_0[0]
CTOF_DEL    ---     0.238 */SLICE_141.C0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_234.CLK to */SLICE_234.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_234.Q1 to */SLICE_705.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[27]
CTOF_DEL    ---     0.238 */SLICE_705.C0 to */SLICE_705.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_705
ROUTE         1   e 0.908 */SLICE_705.F0 to */SLICE_131.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_736
CTOF_DEL    ---     0.238 */SLICE_131.A1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_151.CLK to */SLICE_151.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_151.Q0 to */SLICE_556.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]
CTOF_DEL    ---     0.238 */SLICE_556.B1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B0 to */SLICE_151.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_234.CLK to */SLICE_234.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_234.Q0 to */SLICE_704.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[26]
CTOF_DEL    ---     0.238 */SLICE_704.C0 to */SLICE_704.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_704
ROUTE         1   e 0.908 */SLICE_704.F0 to */SLICE_131.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_720
CTOF_DEL    ---     0.238 */SLICE_131.A0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_160.CLK to */SLICE_160.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_160.Q1 to */SLICE_724.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]
CTOF_DEL    ---     0.238 */SLICE_724.B0 to */SLICE_724.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_724
ROUTE         1   e 0.908 */SLICE_724.F0 to */SLICE_153.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_2_0[0]
CTOF_DEL    ---     0.238 */SLICE_153.D0 to */SLICE_153.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_233.CLK to */SLICE_233.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_233.Q1 to */SLICE_703.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[25]
CTOF_DEL    ---     0.238 */SLICE_703.C0 to */SLICE_703.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_703
ROUTE         1   e 0.908 */SLICE_703.F0 to */SLICE_130.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_704
CTOF_DEL    ---     0.238 */SLICE_130.A1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_195.A0 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_195.A0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_233.CLK to */SLICE_233.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_233.Q0 to */SLICE_702.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[24]
CTOF_DEL    ---     0.238 */SLICE_702.C0 to */SLICE_702.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_702
ROUTE         1   e 0.908 */SLICE_702.F0 to */SLICE_130.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_688
CTOF_DEL    ---     0.238 */SLICE_130.A0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_195.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_195.A1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_194.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_194.C0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_232.CLK to */SLICE_232.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_232.Q1 to */SLICE_701.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[23]
CTOF_DEL    ---     0.238 */SLICE_701.C0 to */SLICE_701.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_701
ROUTE         1   e 0.908 */SLICE_701.F0 to */SLICE_129.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_672
CTOF_DEL    ---     0.238 */SLICE_129.A1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_195.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_195.A1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.908 */SLICE_195.F1 to */SLICE_193.C1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_193.C1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_232.CLK to */SLICE_232.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_232.Q0 to */SLICE_700.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[22]
CTOF_DEL    ---     0.238 */SLICE_700.C0 to */SLICE_700.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_700
ROUTE         1   e 0.908 */SLICE_700.F0 to */SLICE_129.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_656
CTOF_DEL    ---     0.238 */SLICE_129.A0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_262.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_262.D0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_572.CLK to */SLICE_572.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_572.Q0 to */SLICE_560.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast
CTOF_DEL    ---     0.238 */SLICE_560.B1 to */SLICE_560.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE         5   e 0.908 */SLICE_560.F1 to *u/SLICE_75.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_53
CTOF_DEL    ---     0.238 *u/SLICE_75.A0 to *u/SLICE_75.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75
ROUTE         1   e 0.001 *u/SLICE_75.F0 to */SLICE_75.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_43_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_261.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_261.D0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_231.CLK to */SLICE_231.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_231.Q1 to */SLICE_699.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[21]
CTOF_DEL    ---     0.238 */SLICE_699.C0 to */SLICE_699.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_699
ROUTE         1   e 0.908 */SLICE_699.F0 to */SLICE_128.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_640
CTOF_DEL    ---     0.238 */SLICE_128.A1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_257.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_257.D0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_231.CLK to */SLICE_231.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_231.Q0 to */SLICE_698.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[20]
CTOF_DEL    ---     0.238 */SLICE_698.C0 to */SLICE_698.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_698
ROUTE         1   e 0.908 */SLICE_698.F0 to */SLICE_128.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_624
CTOF_DEL    ---     0.238 */SLICE_128.A0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_256.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_256.D0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_230.CLK to */SLICE_230.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_230.Q1 to */SLICE_697.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[19]
CTOF_DEL    ---     0.238 */SLICE_697.C0 to */SLICE_697.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_697
ROUTE         1   e 0.908 */SLICE_697.F0 to */SLICE_127.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_608
CTOF_DEL    ---     0.238 */SLICE_127.A1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_513.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_513.B0 to */SLICE_513.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_513
ROUTE         3   e 0.908 */SLICE_513.F0 to */SLICE_276.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_1
CTOF_DEL    ---     0.238 */SLICE_276.A1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_230.CLK to */SLICE_230.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_230.Q0 to */SLICE_696.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[18]
CTOF_DEL    ---     0.238 */SLICE_696.C0 to */SLICE_696.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_696
ROUTE         1   e 0.908 */SLICE_696.F0 to */SLICE_127.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_592
CTOF_DEL    ---     0.238 */SLICE_127.A0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_288.CLK to */SLICE_288.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_288.Q1 to */SLICE_524.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_524.B1 to */SLICE_524.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524
ROUTE         6   e 0.908 */SLICE_524.F1 to */SLICE_289.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_2
CTOF_DEL    ---     0.238 */SLICE_289.A0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_229.CLK to */SLICE_229.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_229.Q1 to */SLICE_695.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[17]
CTOF_DEL    ---     0.238 */SLICE_695.C0 to */SLICE_695.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_695
ROUTE         1   e 0.908 */SLICE_695.F0 to */SLICE_126.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_576
CTOF_DEL    ---     0.238 */SLICE_126.A1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.908 */SLICE_163.F1 to */SLICE_105.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_105.B0 to */SLICE_105.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105
ROUTE         1   e 0.001 */SLICE_105.F0 to *SLICE_105.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_29_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_229.CLK to */SLICE_229.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_229.Q0 to */SLICE_694.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[16]
CTOF_DEL    ---     0.238 */SLICE_694.C0 to */SLICE_694.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_694
ROUTE         1   e 0.908 */SLICE_694.F0 to */SLICE_126.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_560
CTOF_DEL    ---     0.238 */SLICE_126.A0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_126.CLK to */SLICE_126.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_126.Q1 to */SLICE_694.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]
CTOF_DEL    ---     0.238 */SLICE_694.A0 to */SLICE_694.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_694
ROUTE         1   e 0.908 */SLICE_694.F0 to */SLICE_126.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_560
CTOF_DEL    ---     0.238 */SLICE_126.A0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_313.CLK to */SLICE_313.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_313.Q0 to */SLICE_608.C0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[12]
CTOF_DEL    ---     0.238 */SLICE_608.C0 to */SLICE_608.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F0 to */SLICE_313.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.238 */SLICE_313.C0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_125.CLK to */SLICE_125.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_125.Q1 to */SLICE_616.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]
CTOF_DEL    ---     0.238 */SLICE_616.A1 to */SLICE_616.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_616
ROUTE         1   e 0.908 */SLICE_616.F1 to */SLICE_125.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_82
CTOF_DEL    ---     0.238 */SLICE_125.A0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_312.CLK to */SLICE_312.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_312.Q0 to */SLICE_605.C0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[10]
CTOF_DEL    ---     0.238 */SLICE_605.C0 to */SLICE_605.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F0 to */SLICE_312.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.238 */SLICE_312.C0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_314.CLK to */SLICE_314.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_314.Q0 to */SLICE_608.D1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[14]
CTOF_DEL    ---     0.238 */SLICE_608.D1 to */SLICE_608.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F1 to */SLICE_313.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[13]
CTOF_DEL    ---     0.238 */SLICE_313.C1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_122.CLK to */SLICE_122.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_122.Q1 to */SLICE_688.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]
CTOF_DEL    ---     0.238 */SLICE_688.A0 to */SLICE_688.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_688
ROUTE         1   e 0.908 */SLICE_688.F0 to */SLICE_122.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_432
CTOF_DEL    ---     0.238 */SLICE_122.A0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_313.CLK to */SLICE_313.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_313.Q1 to */SLICE_608.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[13]
CTOF_DEL    ---     0.238 */SLICE_608.D0 to */SLICE_608.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F0 to */SLICE_313.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[12]
CTOF_DEL    ---     0.238 */SLICE_313.C0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_257.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_257.D1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_226.CLK to */SLICE_226.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_226.Q1 to */SLICE_717.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[11]
CTOF_DEL    ---     0.238 */SLICE_717.C0 to */SLICE_717.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_717
ROUTE         1   e 0.908 */SLICE_717.F0 to */SLICE_123.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_84
CTOF_DEL    ---     0.238 */SLICE_123.A1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_257.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_257.D0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_312.CLK to */SLICE_312.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_312.Q1 to */SLICE_605.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[11]
CTOF_DEL    ---     0.238 */SLICE_605.D0 to */SLICE_605.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_605
ROUTE         1   e 0.908 */SLICE_605.F0 to */SLICE_312.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[10]
CTOF_DEL    ---     0.238 */SLICE_312.C0 to */SLICE_312.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312
ROUTE         1   e 0.001 */SLICE_312.F0 to *SLICE_312.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_256.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_256.D1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_225.CLK to */SLICE_225.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_225.Q1 to */SLICE_689.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[9]
CTOF_DEL    ---     0.238 */SLICE_689.C0 to */SLICE_689.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_689
ROUTE         1   e 0.908 */SLICE_689.F0 to */SLICE_122.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_448
CTOF_DEL    ---     0.238 */SLICE_122.A1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_256.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_256.D1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_311.CLK to */SLICE_311.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_311.Q1 to */SLICE_606.D1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[9]
CTOF_DEL    ---     0.238 */SLICE_606.D1 to */SLICE_606.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F1 to */SLICE_311.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.238 */SLICE_311.C0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_256.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_256.D0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_310.CLK to */SLICE_310.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_310.Q1 to */SLICE_607.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[7]
CTOF_DEL    ---     0.238 */SLICE_607.D0 to */SLICE_607.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F0 to */SLICE_310.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[6]
CTOF_DEL    ---     0.238 */SLICE_310.C0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_311.CLK to */SLICE_311.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_311.Q0 to */SLICE_606.C1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[8]
CTOF_DEL    ---     0.238 */SLICE_606.C1 to */SLICE_606.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_606
ROUTE         1   e 0.908 */SLICE_606.F1 to */SLICE_311.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[8]
CTOF_DEL    ---     0.238 */SLICE_311.C0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_309.CLK to */SLICE_309.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_309.Q1 to */SLICE_636.D0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[5]
CTOF_DEL    ---     0.238 */SLICE_636.D0 to */SLICE_636.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE         1   e 0.908 */SLICE_636.F0 to */SLICE_309.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.238 */SLICE_309.C0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_310.CLK to */SLICE_310.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_310.Q0 to */SLICE_607.C0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[6]
CTOF_DEL    ---     0.238 */SLICE_607.C0 to */SLICE_607.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_607
ROUTE         1   e 0.908 */SLICE_607.F0 to */SLICE_310.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[6]
CTOF_DEL    ---     0.238 */SLICE_310.C0 to */SLICE_310.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F0 to *SLICE_310.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_223.CLK to */SLICE_223.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_223.Q1 to */SLICE_685.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[5]
CTOF_DEL    ---     0.238 */SLICE_685.C0 to */SLICE_685.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_685
ROUTE         1   e 0.908 */SLICE_685.F0 to */SLICE_120.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_384
CTOF_DEL    ---     0.238 */SLICE_120.A1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_309.CLK to */SLICE_309.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_309.Q0 to */SLICE_636.C0 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[4]
CTOF_DEL    ---     0.238 */SLICE_636.C0 to */SLICE_636.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE         1   e 0.908 */SLICE_636.F0 to */SLICE_309.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[4]
CTOF_DEL    ---     0.238 */SLICE_309.C0 to */SLICE_309.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309
ROUTE         1   e 0.001 */SLICE_309.F0 to *SLICE_309.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_222.CLK to */SLICE_222.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_222.Q1 to */SLICE_683.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[3]
CTOF_DEL    ---     0.238 */SLICE_683.C0 to */SLICE_683.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_683
ROUTE         1   e 0.908 */SLICE_683.F0 to */SLICE_119.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_352
CTOF_DEL    ---     0.238 */SLICE_119.A1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_260.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_260.D1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_221.CLK to */SLICE_221.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_221.Q0 to */SLICE_680.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[0]
CTOF_DEL    ---     0.238 */SLICE_680.C0 to */SLICE_680.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_680
ROUTE         1   e 0.908 */SLICE_680.F0 to */SLICE_118.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_304
CTOF_DEL    ---     0.238 */SLICE_118.A0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_260.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_260.D0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_602.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[0]
CTOF_DEL    ---     0.238 */SLICE_602.A1 to */SLICE_602.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602
ROUTE         1   e 0.908 */SLICE_602.F1 to */SLICE_140.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4
CTOF_DEL    ---     0.238 */SLICE_140.D0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_260.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_260.D0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_148.CLK to */SLICE_148.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_148.Q1 to */SLICE_725.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]
CTOF_DEL    ---     0.238 */SLICE_725.B0 to */SLICE_725.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_725
ROUTE         1   e 0.908 */SLICE_725.F0 to */SLICE_141.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_2_0[0]
CTOF_DEL    ---     0.238 */SLICE_141.C0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_259.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_259.D1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_151.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_151.B0 to */SLICE_151.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_259.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_259.D0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.D1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_150.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_150.C1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_259.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_259.D0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_641.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_641.B1 to */SLICE_641.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F1 to */SLICE_161.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a2_0_0
CTOF_DEL    ---     0.238 */SLICE_161.D0 to */SLICE_161.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_258.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_258.D1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_195.CLK to */SLICE_195.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_195.Q0 to *u/SLICE_52.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]
CTOF_DEL    ---     0.238 *u/SLICE_52.A1 to *u/SLICE_52.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_52
ROUTE         1   e 0.908 *u/SLICE_52.F1 to */SLICE_195.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[4]
CTOF_DEL    ---     0.238 */SLICE_195.D0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_258.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_258.D0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_194.A1 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_194.A1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_258.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_258.D0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q1 to *u/SLICE_53.A0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]
CTOF_DEL    ---     0.238 *u/SLICE_53.A0 to *u/SLICE_53.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_53
ROUTE         1   e 0.908 *u/SLICE_53.F0 to */SLICE_193.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[1]
CTOF_DEL    ---     0.238 */SLICE_193.D1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_146.CLK to */SLICE_146.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_146.Q0 to */SLICE_548.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]
CTOF_DEL    ---     0.238 */SLICE_548.C0 to */SLICE_548.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_548
ROUTE         1   e 0.908 */SLICE_548.F0 to */SLICE_311.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[9]
CTOF_DEL    ---     0.238 */SLICE_311.B1 to */SLICE_311.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F1 to *SLICE_311.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q0 to *u/SLICE_54.A1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]
CTOF_DEL    ---     0.238 *u/SLICE_54.A1 to *u/SLICE_54.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_54
ROUTE         1   e 0.908 *u/SLICE_54.F1 to */SLICE_193.D0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_s[0]
CTOF_DEL    ---     0.238 */SLICE_193.D0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_145.CLK to */SLICE_145.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_145.Q0 to */SLICE_546.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]
CTOF_DEL    ---     0.238 */SLICE_546.C0 to */SLICE_546.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_546
ROUTE         1   e 0.908 */SLICE_546.F0 to */SLICE_310.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[7]
CTOF_DEL    ---     0.238 */SLICE_310.B1 to */SLICE_310.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310
ROUTE         1   e 0.001 */SLICE_310.F1 to *SLICE_310.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_326 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q0 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_325.Q0 to */SLICE_621.A1 mg5ahub/bit_count_0
CTOF_DEL    ---     0.238 */SLICE_621.A1 to */SLICE_621.F1 mg5ahub/SLICE_621
ROUTE         1   e 0.908 */SLICE_621.F1 to */SLICE_326.C1 mg5ahub/un8_bit_count_p4
CTOF_DEL    ---     0.238 */SLICE_326.C1 to */SLICE_326.F1 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F1 to *SLICE_326.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_122.CLK to */SLICE_122.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_122.Q0 to */SLICE_687.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]
CTOF_DEL    ---     0.238 */SLICE_687.A0 to */SLICE_687.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_687
ROUTE         1   e 0.908 */SLICE_687.F0 to */SLICE_121.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_416
CTOF_DEL    ---     0.238 */SLICE_121.A1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_263.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_263.D0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_143.CLK to */SLICE_143.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_143.Q0 to */SLICE_542.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]
CTOF_DEL    ---     0.238 */SLICE_542.C0 to */SLICE_542.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_542
ROUTE         1   e 0.908 */SLICE_542.F0 to */SLICE_308.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[3]
CTOF_DEL    ---     0.238 */SLICE_308.B1 to */SLICE_308.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F1 to *SLICE_308.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_260.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_260.D1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_119.CLK to */SLICE_119.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_119.Q1 to */SLICE_682.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]
CTOF_DEL    ---     0.238 */SLICE_682.A0 to */SLICE_682.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_682
ROUTE         1   e 0.908 */SLICE_682.F0 to */SLICE_119.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_336
CTOF_DEL    ---     0.238 */SLICE_119.A0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_259.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_259.D1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_142.CLK to */SLICE_142.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_142.Q1 to */SLICE_539.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]
CTOF_DEL    ---     0.238 */SLICE_539.B0 to */SLICE_539.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_539
ROUTE         1   e 0.908 */SLICE_539.F0 to */SLICE_308.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[2]
CTOF_DEL    ---     0.238 */SLICE_308.B0 to */SLICE_308.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308
ROUTE         1   e 0.001 */SLICE_308.F0 to *SLICE_308.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_258.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_258.D1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_262.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_262.D0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_257.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_257.D1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_261.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_261.D1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_228.CLK to */SLICE_228.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_228.Q1 to */SLICE_693.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[15]
CTOF_DEL    ---     0.238 */SLICE_693.C0 to */SLICE_693.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_693
ROUTE         1   e 0.908 */SLICE_693.F0 to */SLICE_125.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_544
CTOF_DEL    ---     0.238 */SLICE_125.A1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_261.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_261.D1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_313.CLK to */SLICE_313.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_313.Q1 to */SLICE_608.C1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[13]
CTOF_DEL    ---     0.238 */SLICE_608.C1 to */SLICE_608.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_608
ROUTE         1   e 0.908 */SLICE_608.F1 to */SLICE_313.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[13]
CTOF_DEL    ---     0.238 */SLICE_313.C1 to */SLICE_313.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F1 to *SLICE_313.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_261.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_261.D0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to */SLICE_602.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2]
CTOF_DEL    ---     0.238 */SLICE_602.B1 to */SLICE_602.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602
ROUTE         1   e 0.908 */SLICE_602.F1 to */SLICE_140.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4
CTOF_DEL    ---     0.238 */SLICE_140.D0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_307.CLK to */SLICE_307.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (from jtaghub16_jtck)
ROUTE        12   e 0.908 */SLICE_307.Q1 to */SLICE_609.C1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[1]
CTOF_DEL    ---     0.238 */SLICE_609.C1 to */SLICE_609.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_609
ROUTE         1   e 0.908 */SLICE_609.F1 to */SLICE_307.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[1]
CTOF_DEL    ---     0.238 */SLICE_307.C1 to */SLICE_307.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307
ROUTE         1   e 0.001 */SLICE_307.F1 to *SLICE_307.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_641.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_641.C1 to */SLICE_641.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_641
ROUTE         1   e 0.908 */SLICE_641.F1 to */SLICE_161.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5_f0_0_a2_0_0
CTOF_DEL    ---     0.238 */SLICE_161.D0 to */SLICE_161.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_119.CLK to */SLICE_119.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_119.Q0 to */SLICE_681.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]
CTOF_DEL    ---     0.238 */SLICE_681.A0 to */SLICE_681.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_681
ROUTE         1   e 0.908 */SLICE_681.F0 to */SLICE_118.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_320
CTOF_DEL    ---     0.238 */SLICE_118.A1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_193.A0 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr
CTOF_DEL    ---     0.238 */SLICE_193.A0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_263.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_263.D1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_326 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q1 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_325.Q1 to */SLICE_621.B1 mg5ahub/bit_count_1
CTOF_DEL    ---     0.238 */SLICE_621.B1 to */SLICE_621.F1 mg5ahub/SLICE_621
ROUTE         1   e 0.908 */SLICE_621.F1 to */SLICE_326.C1 mg5ahub/un8_bit_count_p4
CTOF_DEL    ---     0.238 */SLICE_326.C1 to */SLICE_326.F1 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F1 to *SLICE_326.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.D1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_150.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]
CTOF_DEL    ---     0.238 */SLICE_150.C0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_152.CLK to */SLICE_152.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_152.Q0 to */SLICE_556.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]
CTOF_DEL    ---     0.238 */SLICE_556.C1 to */SLICE_556.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_556
ROUTE        52   e 0.908 */SLICE_556.F1 to */SLICE_150.B0 Test_reveal_coretop_instance/test_la0_inst_0/tr_bit_0
CTOF_DEL    ---     0.238 */SLICE_150.B0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_514.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_514.A1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_263.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_263.D0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_514.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_514.B1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_262.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_262.D1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_274.CLK to */SLICE_274.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_274.Q0 to */SLICE_514.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_514.C1 to */SLICE_514.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE        18   e 0.908 */SLICE_514.F1 to */SLICE_263.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active21
CTOF_DEL    ---     0.238 */SLICE_263.D0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.733ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (2.656ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_132.CLK to */SLICE_132.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_132.Q0 to */SLICE_705.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]
CTOF_DEL    ---     0.238 */SLICE_705.A0 to */SLICE_705.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_705
ROUTE         1   e 0.908 */SLICE_705.F0 to */SLICE_131.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_736
CTOF_DEL    ---     0.238 */SLICE_131.A1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    2.656   (31.6% logic, 68.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_48.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_51.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_718.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_718.A0 to */SLICE_718.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718
ROUTE         1   e 0.908 */SLICE_718.F0 to */SLICE_615.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_116.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_50.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_117.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_628.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_99.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_99.A1 to *u/SLICE_99.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         2   e 0.908 *u/SLICE_99.F1 to */SLICE_592.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_109.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_602.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_108.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_128.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_125.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_126.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_137.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_121.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_118.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_136.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_119.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_120.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_554.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_554.B0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_155.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_127.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_554.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_554.B0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_157.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_554.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_554.B0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_153.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_138.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_129.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_122.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_554.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_554.B0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_160.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_123.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_133.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_124.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_639.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_170 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_170.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_554.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_554.B0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_158.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_554.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_554.B0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_156.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_554.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_554.B0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_154.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_551.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_139.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_76.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_132.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_130.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_554.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_554.B0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_159.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_134.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to *u/SLICE_49.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_135.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_79.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_77.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_315 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_315.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_85.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_85.A1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_538.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_72.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_73.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_560.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_560.B0 to */SLICE_560.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560
ROUTE        28   e 0.908 */SLICE_560.F0 to */SLICE_131.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_87 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_722.A0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_722.A0 to */SLICE_722.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_722
ROUTE         1   e 0.908 */SLICE_722.F0 to *u/SLICE_87.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_547.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to */SLICE_568.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_636.B1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 */SLICE_636.B1 to */SLICE_636.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636
ROUTE        17   e 0.908 */SLICE_636.F1 to *u/SLICE_78.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_99.A1 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_99.A1 to *u/SLICE_99.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         2   e 0.908 *u/SLICE_99.F1 to */SLICE_638.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_337 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_337.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_514.D0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_514.D0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_514.D0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_514.D0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_514.D0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_514.D0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_514.D0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_514.D0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.D1 to *u/SLICE_85.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         4   e 0.908 *u/SLICE_85.F1 to */SLICE_538.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0] (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_162.Q0 to */SLICE_554.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_554.D0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_153.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_515.Q0 to */SLICE_514.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_514.C0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_262.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_515.Q0 to */SLICE_514.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_514.C0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_260.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_515.Q0 to */SLICE_514.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_514.C0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_258.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_515.Q0 to */SLICE_514.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_514.C0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_256.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to *u/SLICE_99.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 *u/SLICE_99.B1 to *u/SLICE_99.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         2   e 0.908 *u/SLICE_99.F1 to */SLICE_592.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_162.Q0 to */SLICE_554.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_554.D0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_159.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_329 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_329.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_334 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_334.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_328 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_328.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_330 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_330.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_332 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_332.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to *u/SLICE_99.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 *u/SLICE_99.D1 to *u/SLICE_99.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         2   e 0.908 *u/SLICE_99.F1 to */SLICE_638.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to *u/SLICE_99.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 *u/SLICE_99.B1 to *u/SLICE_99.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         2   e 0.908 *u/SLICE_99.F1 to */SLICE_638.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_162.Q0 to */SLICE_554.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_554.D0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_158.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_162.Q0 to */SLICE_554.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_554.D0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_154.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_331 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_331.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_333 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_333.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_335 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_335.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q1 to */SLICE_515.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_515.D0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_287.CLK to */SLICE_287.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_287.Q0 to */SLICE_527.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_enz
CTOF_DEL    ---     0.238 */SLICE_527.C0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to *u/SLICE_99.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 *u/SLICE_99.C1 to *u/SLICE_99.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         2   e 0.908 *u/SLICE_99.F1 to */SLICE_638.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to *u/SLICE_99.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 *u/SLICE_99.C1 to *u/SLICE_99.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         2   e 0.908 *u/SLICE_99.F1 to */SLICE_592.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_162.Q0 to */SLICE_554.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_554.D0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_156.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_192.Q1 to */SLICE_592.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2
CTOF_DEL    ---     0.238 */SLICE_592.B1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_336 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_742.B0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_742.B0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_336.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_514.D0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_514.D0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_514.D0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_514.D0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_514.D0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_514.D0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_514.D0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_514.D0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q0 to */SLICE_515.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_515.C0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_40.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_527.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_527.A0 to */SLICE_527.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527
ROUTE         1   e 0.908 */SLICE_527.F0 to */SLICE_287.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1 (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_162.Q0 to */SLICE_554.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_554.D0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_157.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_37.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_515.Q0 to */SLICE_514.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_514.C0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_263.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_515.Q0 to */SLICE_514.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_514.C0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_261.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_515.Q0 to */SLICE_514.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_514.C0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_259.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_515.Q0 to */SLICE_514.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_514.C0 to */SLICE_514.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514
ROUTE         8   e 0.908 */SLICE_514.F0 to */SLICE_257.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_41.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_35.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_523.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_523.C0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_39.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_43.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to *u/SLICE_99.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 *u/SLICE_99.D1 to *u/SLICE_99.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         2   e 0.908 *u/SLICE_99.F1 to */SLICE_592.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_523.D0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_523.D0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_99.CLK to *u/SLICE_99.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *u/SLICE_99.Q0 to */SLICE_718.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1
CTOF_DEL    ---     0.238 */SLICE_718.C0 to */SLICE_718.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718
ROUTE         1   e 0.908 */SLICE_718.F0 to */SLICE_615.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_36.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_162.Q0 to */SLICE_554.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_554.D0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_155.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_38.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_286.CLK to */SLICE_286.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_286.Q0 to */SLICE_523.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active
CTOF_DEL    ---     0.238 */SLICE_523.B0 to */SLICE_523.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523
ROUTE         9   e 0.908 */SLICE_523.F0 to *1/SLICE_42.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.643ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (2.417ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_162.Q0 to */SLICE_554.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_554.D0 to */SLICE_554.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554
ROUTE         8   e 0.908 */SLICE_554.F0 to */SLICE_160.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.568ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (2.417ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.908 *u/SLICE_85.F0 to */SLICE_515.M0 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr (to jtaghub16_jtck)
                  --------
                    2.417   (24.9% logic, 75.1% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.527ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (2.450ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_547.CLK to */SLICE_547.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (from jtaghub16_jtck)
ROUTE         6   e 0.232 */SLICE_547.Q0 to */SLICE_547.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0
CTOF_DEL    ---     0.238 */SLICE_547.B1 to */SLICE_547.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.232 */SLICE_547.F1 to */SLICE_547.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m1_0[8]
CTOF_DEL    ---     0.238 */SLICE_547.B0 to */SLICE_547.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547
ROUTE         1   e 0.908 */SLICE_547.F0 to */SLICE_311.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[8]
CTOF_DEL    ---     0.238 */SLICE_311.B0 to */SLICE_311.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311
ROUTE         1   e 0.001 */SLICE_311.F0 to *SLICE_311.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i (to jtaghub16_jtck)
                  --------
                    2.450   (44.0% logic, 56.0% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.527ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (2.450ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_551.CLK to */SLICE_551.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (from jtaghub16_jtck)
ROUTE         7   e 0.232 */SLICE_551.Q0 to */SLICE_551.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0
CTOF_DEL    ---     0.238 */SLICE_551.B1 to */SLICE_551.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.232 */SLICE_551.F1 to */SLICE_551.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11_m0[12]
CTOF_DEL    ---     0.238 */SLICE_551.B0 to */SLICE_551.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551
ROUTE         1   e 0.908 */SLICE_551.F0 to */SLICE_313.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_11[12]
CTOF_DEL    ---     0.238 */SLICE_313.B0 to */SLICE_313.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313
ROUTE         1   e 0.001 */SLICE_313.F0 to *SLICE_313.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i (to jtaghub16_jtck)
                  --------
                    2.450   (44.0% logic, 56.0% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.527ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (2.450ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_525.Q0 to */SLICE_525.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_525.B1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_289.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_289.A1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.232 */SLICE_289.F1 to */SLICE_289.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_289.D0 to */SLICE_289.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         1   e 0.001 */SLICE_289.F0 to *SLICE_289.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1 (to jtaghub16_jtck)
                  --------
                    2.450   (44.0% logic, 56.0% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_90.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_90.B0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.232 *u/SLICE_90.F0 to *u/SLICE_90.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.238 *u/SLICE_90.B1 to *u/SLICE_90.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         1   e 0.232 *u/SLICE_90.F1 to *u/SLICE_90.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59 (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_242.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_230.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_238.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_223.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_222.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_234.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to *u/SLICE_90.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 *u/SLICE_90.C0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.232 *u/SLICE_90.F0 to *u/SLICE_90.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa
CTOF_DEL    ---     0.238 *u/SLICE_90.B1 to *u/SLICE_90.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         1   e 0.232 *u/SLICE_90.F1 to *u/SLICE_90.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59 (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_226.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_538.CLK to */SLICE_538.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_538.Q0 to */SLICE_538.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en
CTOF_DEL    ---     0.238 */SLICE_538.B1 to */SLICE_538.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 0.232 */SLICE_538.F1 to */SLICE_538.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_0_o2_0
CTOF_DEL    ---     0.238 */SLICE_538.D0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_152.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_225.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_538.CLK to */SLICE_538.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_538.Q0 to */SLICE_538.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en
CTOF_DEL    ---     0.238 */SLICE_538.B1 to */SLICE_538.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 0.232 */SLICE_538.F1 to */SLICE_538.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_0_o2_0
CTOF_DEL    ---     0.238 */SLICE_538.D0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_150.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_221.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_241.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_538.CLK to */SLICE_538.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_538.Q0 to */SLICE_538.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en
CTOF_DEL    ---     0.238 */SLICE_538.B1 to */SLICE_538.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         1   e 0.232 */SLICE_538.F1 to */SLICE_538.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cntlde_0_o2_0
CTOF_DEL    ---     0.238 */SLICE_538.D0 to */SLICE_538.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538
ROUTE         3   e 0.908 */SLICE_538.F0 to */SLICE_151.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_239.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_240.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_237.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_236.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_235.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_232.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_233.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_228.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_231.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_224.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_229.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_525.Q0 to */SLICE_525.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_525.B1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.232 */SLICE_525.F1 to */SLICE_525.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_525.D0 to */SLICE_525.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         1   e 0.908 */SLICE_525.F0 to */SLICE_286.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.232 */SLICE_592.Q0 to */SLICE_592.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_592.A0 to */SLICE_592.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE         1   e 0.232 */SLICE_592.F0 to */SLICE_592.D1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i_1
CTOF_DEL    ---     0.238 */SLICE_592.D1 to */SLICE_592.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592
ROUTE        22   e 0.908 */SLICE_592.F1 to */SLICE_227.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.437ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (2.211ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_515.CLK to */SLICE_515.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_515.Q0 to */SLICE_515.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1
CTOF_DEL    ---     0.238 */SLICE_515.B1 to */SLICE_515.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         2   e 0.232 */SLICE_515.F1 to */SLICE_515.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active6
CTOF_DEL    ---     0.238 */SLICE_515.A0 to */SLICE_515.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515
ROUTE         1   e 0.908 */SLICE_515.F0 to */SLICE_274.CE Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i (to jtaghub16_jtck)
                  --------
                    2.211   (37.9% logic, 62.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.278ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (2.201ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_51.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.550 *u/SLICE_51.B0 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_50.FCI to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_49.FCI to *u/SLICE_49.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F1 to */SLICE_49.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    2.201   (58.6% logic, 41.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.276ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (2.199ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_51.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.550 *u/SLICE_51.B0 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_50.FCI to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_49.FCI to */SLICE_49.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_48.FCI to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    2.199   (58.5% logic, 41.5% route), 5 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    2.218ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_726 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (2.141ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_726.CLK to */SLICE_726.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_726 (from ipClk_c)
ROUTE         3   e 0.232 */SLICE_726.Q0 to */SLICE_726.A0 Test_reveal_coretop_instance/test_la0_inst_0/even_parity
CTOF_DEL    ---     0.238 */SLICE_726.A0 to */SLICE_726.F0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_726
ROUTE         1   e 0.908 */SLICE_726.F0 to */SLICE_104.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/g0_6_1
CTOOFX_DEL  ---     0.399 */SLICE_104.C1 to *LICE_104.OFX0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104
ROUTE         1   e 0.001 *LICE_104.OFX0 to *SLICE_104.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5 (to jtaghub16_jtck)
                  --------
                    2.141   (46.7% logic, 53.3% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.210ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (2.133ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to *u/SLICE_50.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
C0TOFCO_DE  ---     0.550 *u/SLICE_50.A0 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_49.FCI to *u/SLICE_49.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F1 to */SLICE_49.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    2.133   (57.3% logic, 42.7% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.210ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (2.133ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_51.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.550 *u/SLICE_51.B0 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOF1_DE  ---     0.310 */SLICE_50.FCI to *u/SLICE_50.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F1 to */SLICE_50.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    2.133   (57.3% logic, 42.7% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.208ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (2.131ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to *u/SLICE_50.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
C0TOFCO_DE  ---     0.550 *u/SLICE_50.A0 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_49.FCI to */SLICE_49.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_48.FCI to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    2.131   (57.3% logic, 42.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.208ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (2.131ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_51.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.550 *u/SLICE_51.B0 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_50.FCI to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_49.FCI to *u/SLICE_49.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F0 to */SLICE_49.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    2.131   (57.3% logic, 42.7% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.140ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (2.063ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to *u/SLICE_50.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
C0TOFCO_DE  ---     0.550 *u/SLICE_50.A0 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_49.FCI to *u/SLICE_49.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F0 to */SLICE_49.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    2.063   (55.9% logic, 44.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.140ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (2.063ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_51.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
C0TOFCO_DE  ---     0.550 *u/SLICE_51.B0 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOF0_DE  ---     0.240 */SLICE_50.FCI to *u/SLICE_50.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F0 to */SLICE_50.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[1] (to jtaghub16_jtck)
                  --------
                    2.063   (55.9% logic, 44.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_638.CLK to */SLICE_638.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (from jtaghub16_jtck)
ROUTE        13   e 0.908 */SLICE_638.Q0 to */SLICE_161.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w
CTOF_DEL    ---     0.238 */SLICE_161.D1 to */SLICE_161.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE        16   e 0.232 */SLICE_161.F1 to */SLICE_161.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg33
CTOF_DEL    ---     0.238 */SLICE_161.B0 to */SLICE_161.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_163.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 */SLICE_163.A1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.232 */SLICE_163.F1 to */SLICE_163.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_163.A0 to */SLICE_163.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F0 to *SLICE_163.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_49_i (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_289.CLK to */SLICE_289.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_289.Q0 to */SLICE_289.D1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_289.D1 to */SLICE_289.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289
ROUTE         3   e 0.908 */SLICE_289.F1 to */SLICE_288.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_0
CTOF_DEL    ---     0.238 */SLICE_288.D0 to */SLICE_288.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288
ROUTE         1   e 0.001 */SLICE_288.F0 to *SLICE_288.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0] (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to */SLICE_163.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_163.C1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.232 */SLICE_163.F1 to */SLICE_163.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_163.A0 to */SLICE_163.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F0 to *SLICE_163.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_49_i (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.908 *u/SLICE_72.Q1 to */SLICE_140.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr[1]
CTOF_DEL    ---     0.238 */SLICE_140.A1 to */SLICE_140.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.232 */SLICE_140.F1 to */SLICE_140.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3
CTOF_DEL    ---     0.238 */SLICE_140.C0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.232 */SLICE_602.Q0 to */SLICE_602.C1 Test_reveal_coretop_instance/test_la0_inst_0/addr[4]
CTOF_DEL    ---     0.238 */SLICE_602.C1 to */SLICE_602.F1 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602
ROUTE         1   e 0.908 */SLICE_602.F1 to */SLICE_140.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_4
CTOF_DEL    ---     0.238 */SLICE_140.D0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_306.Q0 to */SLICE_162.C1 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_162.C1 to */SLICE_162.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.232 */SLICE_162.F1 to */SLICE_162.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.238 */SLICE_162.A0 to */SLICE_162.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_161.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_161.C1 to */SLICE_161.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE        16   e 0.232 */SLICE_161.F1 to */SLICE_161.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg33
CTOF_DEL    ---     0.238 */SLICE_161.B0 to */SLICE_161.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to */SLICE_140.B1 Test_reveal_coretop_instance/test_la0_inst_0/addr[12]
CTOF_DEL    ---     0.238 */SLICE_140.B1 to */SLICE_140.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.232 */SLICE_140.F1 to */SLICE_140.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3
CTOF_DEL    ---     0.238 */SLICE_140.C0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_315 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_315.CLK to */SLICE_315.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_315 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_315.Q0 to */SLICE_314.D1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[15]
CTOF_DEL    ---     0.238 */SLICE_314.D1 to */SLICE_314.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.232 */SLICE_314.F1 to */SLICE_314.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.238 */SLICE_314.C0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to */SLICE_163.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 */SLICE_163.B1 to */SLICE_163.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         6   e 0.232 */SLICE_163.F1 to */SLICE_163.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60
CTOF_DEL    ---     0.238 */SLICE_163.A0 to */SLICE_163.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F0 to *SLICE_163.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_49_i (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_195.A1 Test_reveal_coretop_instance/test_la0_inst_0/addr_15
CTOF_DEL    ---     0.238 */SLICE_195.A1 to */SLICE_195.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         6   e 0.232 */SLICE_195.F1 to */SLICE_195.C0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr19
CTOF_DEL    ---     0.238 */SLICE_195.C0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_91.Q0 to */SLICE_162.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1
CTOF_DEL    ---     0.238 */SLICE_162.A1 to */SLICE_162.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.232 */SLICE_162.F1 to */SLICE_162.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_99
CTOF_DEL    ---     0.238 */SLICE_162.A0 to */SLICE_162.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    2.057ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286 (1.980ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_525.Q0 to */SLICE_525.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_525.B1 to */SLICE_525.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525
ROUTE         5   e 0.908 */SLICE_525.F1 to */SLICE_286.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active46
CTOF_DEL    ---     0.238 */SLICE_286.C0 to */SLICE_286.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286
ROUTE         1   e 0.001 */SLICE_286.F0 to *SLICE_286.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    1.980   (42.4% logic, 57.6% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_555.Q0 to */SLICE_555.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_555.C0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_144.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_337 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_337.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_555.Q0 to */SLICE_555.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_555.C0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_145.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_555.Q0 to */SLICE_555.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_555.C0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_142.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.232 */SLICE_191.Q0 to */SLICE_191.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.238 */SLICE_191.B1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_193.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_329 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_329.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_331 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_331.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.232 */SLICE_191.Q0 to */SLICE_191.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.238 */SLICE_191.B1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_195.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_555.Q0 to */SLICE_555.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_555.C0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_148.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_328 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_328.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_330 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_330.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_332 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_332.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_334 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_334.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_336 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_336.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_555.Q0 to */SLICE_555.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_555.C0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_146.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_333 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_333.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay mg5ahub/SLICE_742 to mg5ahub/SLICE_335 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_742.CLK to */SLICE_742.Q0 mg5ahub/SLICE_742 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_742.Q0 to */SLICE_742.A0 mg5ahub/jce1_d1
CTOF_DEL    ---     0.238 */SLICE_742.A0 to */SLICE_742.F0 mg5ahub/SLICE_742
ROUTE        10   e 0.908 */SLICE_742.F0 to */SLICE_335.CE mg5ahub/N_45_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_718.CLK to */SLICE_718.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_718.Q0 to */SLICE_718.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3
CTOF_DEL    ---     0.238 */SLICE_718.B0 to */SLICE_718.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718
ROUTE         1   e 0.908 */SLICE_718.F0 to */SLICE_615.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_555.Q0 to */SLICE_555.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_555.C0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_147.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_555.Q0 to */SLICE_555.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_555.C0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_141.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_555.Q0 to */SLICE_555.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_555.C0 to */SLICE_555.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555
ROUTE         8   e 0.908 */SLICE_555.F0 to */SLICE_143.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         5   e 0.908 */SLICE_103.Q0 to *u/SLICE_90.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]
CTOF_DEL    ---     0.238 *u/SLICE_90.C1 to *u/SLICE_90.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         1   e 0.232 *u/SLICE_90.F1 to *u/SLICE_90.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_103.CLK to */SLICE_103.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_103 (from ipClk_c)
ROUTE         4   e 0.908 */SLICE_103.Q1 to *u/SLICE_90.D1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]
CTOF_DEL    ---     0.238 *u/SLICE_90.D1 to *u/SLICE_90.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         1   e 0.232 *u/SLICE_90.F1 to *u/SLICE_90.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59 (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.967ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (1.741ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.232 */SLICE_191.Q0 to */SLICE_191.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.238 */SLICE_191.B1 to */SLICE_191.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         3   e 0.908 */SLICE_191.F1 to */SLICE_194.CE Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i (to jtaghub16_jtck)
                  --------
                    1.741   (34.5% logic, 65.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.874ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.797ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.797   (86.7% logic, 13.3% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.872ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.795ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.795   (86.6% logic, 13.4% route), 9 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.806ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.729ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.729   (86.2% logic, 13.8% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.806ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.729ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.729   (86.2% logic, 13.8% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.804ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.727ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.727   (86.2% logic, 13.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.804ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.727ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.727   (86.2% logic, 13.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.759ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.682ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.682   (85.7% logic, 14.3% route), 9 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.757ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.680ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.680   (85.7% logic, 14.3% route), 10 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.748ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_327 (1.671ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_327.A0 mg5ahub/jshift_d1
CTOOFX_DEL  ---     0.399 */SLICE_327.A0 to *LICE_327.OFX0 mg5ahub/SLICE_327
ROUTE         1   e 0.001 *LICE_327.OFX0 to *SLICE_327.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.671   (45.6% logic, 54.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.748ns delay mg5ahub/SLICE_326 to mg5ahub/SLICE_327 (1.671ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_326.CLK to */SLICE_326.Q0 mg5ahub/SLICE_326 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_326.Q0 to */SLICE_327.C1 mg5ahub/bit_count_2
CTOOFX_DEL  ---     0.399 */SLICE_327.C1 to *LICE_327.OFX0 mg5ahub/SLICE_327
ROUTE         1   e 0.001 *LICE_327.OFX0 to *SLICE_327.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.671   (45.6% logic, 54.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.748ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_327 (1.671ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q1 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_325.Q1 to */SLICE_327.D1 mg5ahub/bit_count_1
CTOOFX_DEL  ---     0.399 */SLICE_327.D1 to *LICE_327.OFX0 mg5ahub/SLICE_327
ROUTE         1   e 0.001 *LICE_327.OFX0 to *SLICE_327.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.671   (45.6% logic, 54.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.738ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.661ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.661   (85.7% logic, 14.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.738ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.661ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.661   (85.7% logic, 14.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.738ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.661ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.661   (85.7% logic, 14.3% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.736ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.659ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.659   (85.7% logic, 14.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.736ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.659ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.659   (85.7% logic, 14.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.736ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.659ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.659   (85.7% logic, 14.3% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.716ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (1.639ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to *u/SLICE_50.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF1_DEL   ---     0.367 *u/SLICE_50.A0 to *u/SLICE_50.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F1 to */SLICE_50.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    1.639   (44.5% logic, 55.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.716ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (1.639ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_51.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF1_DEL   ---     0.367 *u/SLICE_51.B0 to *u/SLICE_51.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 *u/SLICE_51.F1 to */SLICE_51.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[0] (to jtaghub16_jtck)
                  --------
                    1.639   (44.5% logic, 55.5% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.691ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.614ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.614   (85.2% logic, 14.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.691ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.614ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.614   (85.2% logic, 14.8% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.689ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.612ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.612   (85.1% logic, 14.9% route), 9 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.689ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.612ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.612   (85.1% logic, 14.9% route), 9 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.670ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.593ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF1_DE  ---     0.310 */SLICE_39.FCI to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    1.593   (85.2% logic, 14.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.670ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.593ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.593   (85.2% logic, 14.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.670ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.593ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.593   (85.2% logic, 14.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.670ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.593ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
C0TOFCO_DE  ---     0.550 *1/SLICE_39.A0 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.593   (85.2% logic, 14.8% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.668ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.591ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.591   (85.1% logic, 14.9% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.668ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.591ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
C0TOFCO_DE  ---     0.550 *1/SLICE_39.A0 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.591   (85.1% logic, 14.9% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.668ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.591ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.591   (85.1% logic, 14.9% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.668ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.591ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.591   (85.1% logic, 14.9% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.623ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.546ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.546   (84.6% logic, 15.4% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.623ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.546ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.546   (84.6% logic, 15.4% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.623ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.546ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.546   (84.6% logic, 15.4% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.621ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.544ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.544   (84.5% logic, 15.5% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.621ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.544ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.544   (84.5% logic, 15.5% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.621ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.544ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.544   (84.5% logic, 15.5% route), 8 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.602ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.525ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF1_DE  ---     0.310 */SLICE_40.FCI to *1/SLICE_40.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F1 to */SLICE_40.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6] (to jtaghub16_jtck)
                  --------
                    1.525   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.602ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_66 (1.525ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q0 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q0 to *b/SLICE_68.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.550 *b/SLICE_68.C0 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.310 */SLICE_66.FCI to *b/SLICE_66.F1 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F1 to */SLICE_66.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.525   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.602ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.525ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q0 to *1/SLICE_38.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
C0TOFCO_DE  ---     0.550 *1/SLICE_38.A0 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.525   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.602ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.525ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.525   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.602ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.525ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF1_DE  ---     0.310 */SLICE_39.FCI to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    1.525   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.602ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.525ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
C0TOFCO_DE  ---     0.550 *1/SLICE_39.A0 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.525   (84.6% logic, 15.4% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.600ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_65 (1.523ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q0 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q0 to *b/SLICE_68.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.550 *b/SLICE_68.C0 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.067 */SLICE_66.FCI to */SLICE_66.FCO mg5ahub/SLICE_66
ROUTE         1   e 0.001 */SLICE_66.FCO to */SLICE_65.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.240 */SLICE_65.FCI to *b/SLICE_65.F0 mg5ahub/SLICE_65
ROUTE         1   e 0.001 *b/SLICE_65.F0 to */SLICE_65.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.523   (84.5% logic, 15.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.600ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.523ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
C0TOFCO_DE  ---     0.550 *1/SLICE_39.A0 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.523   (84.5% logic, 15.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.600ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.523ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.523   (84.5% logic, 15.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.600ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.523ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q0 to *1/SLICE_38.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
C0TOFCO_DE  ---     0.550 *1/SLICE_38.A0 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.523   (84.5% logic, 15.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.600ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.523ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF0_DE  ---     0.240 */SLICE_39.FCI to *1/SLICE_39.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F0 to */SLICE_39.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7] (to jtaghub16_jtck)
                  --------
                    1.523   (84.5% logic, 15.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.600ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.523ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.523   (84.5% logic, 15.5% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.592ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_327 (1.515ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q0 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_325.Q0 to */SLICE_327.M0 mg5ahub/bit_count_0
MTOOFX_DEL  ---     0.243 */SLICE_327.M0 to *LICE_327.OFX0 mg5ahub/SLICE_327
ROUTE         1   e 0.001 *LICE_327.OFX0 to *SLICE_327.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    1.515   (40.0% logic, 60.0% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_90.B0 jtaghub16_ip_enable0
CTOF_DEL    ---     0.238 *u/SLICE_90.B0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.001 *u/SLICE_90.F0 to */SLICE_90.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_191.Q0 to */SLICE_194.B0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.238 */SLICE_194.B0 to */SLICE_194.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F0 to *SLICE_194.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to *u/SLICE_48.A0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 *u/SLICE_48.A0 to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_271 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_271.CLK to */SLICE_271.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_271 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_271.Q1 to */SLICE_263.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]
CTOF_DEL    ---     0.238 */SLICE_263.B1 to */SLICE_263.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F1 to *SLICE_263.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_269 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_269.CLK to */SLICE_269.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_269 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_269.Q1 to */SLICE_261.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]
CTOF_DEL    ---     0.238 */SLICE_261.B1 to */SLICE_261.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F1 to *SLICE_261.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_267 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_267.CLK to */SLICE_267.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_267 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_267.Q1 to */SLICE_259.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]
CTOF_DEL    ---     0.238 */SLICE_259.B1 to */SLICE_259.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F1 to *SLICE_259.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_265 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_265.CLK to */SLICE_265.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_265 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_265.Q1 to */SLICE_257.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]
CTOF_DEL    ---     0.238 */SLICE_257.B1 to */SLICE_257.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F1 to *SLICE_257.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_144.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_144.A1 to */SLICE_144.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[7] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_142.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_142.A1 to */SLICE_142.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[3] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_271 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_271.CLK to */SLICE_271.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_271 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_271.Q0 to */SLICE_263.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]
CTOF_DEL    ---     0.238 */SLICE_263.B0 to */SLICE_263.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263
ROUTE         1   e 0.001 */SLICE_263.F0 to *SLICE_263.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_269 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_269.CLK to */SLICE_269.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_269 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_269.Q0 to */SLICE_261.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]
CTOF_DEL    ---     0.238 */SLICE_261.B0 to */SLICE_261.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261
ROUTE         1   e 0.001 */SLICE_261.F0 to *SLICE_261.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_267 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_267.CLK to */SLICE_267.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_267 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_267.Q0 to */SLICE_259.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]
CTOF_DEL    ---     0.238 */SLICE_259.B0 to */SLICE_259.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259
ROUTE         1   e 0.001 */SLICE_259.F0 to *SLICE_259.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_265 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_265.CLK to */SLICE_265.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_265 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_265.Q0 to */SLICE_257.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]
CTOF_DEL    ---     0.238 */SLICE_257.B0 to */SLICE_257.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257
ROUTE         1   e 0.001 */SLICE_257.F0 to *SLICE_257.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_236.CLK to */SLICE_236.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_236.Q0 to */SLICE_132.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[30]
CTOF_DEL    ---     0.238 */SLICE_132.C1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_235.CLK to */SLICE_235.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_235.Q0 to */SLICE_131.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[28]
CTOF_DEL    ---     0.238 */SLICE_131.C1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_234.CLK to */SLICE_234.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_234.Q0 to */SLICE_130.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[26]
CTOF_DEL    ---     0.238 */SLICE_130.C1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_155.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_155.B0 to */SLICE_155.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_233.CLK to */SLICE_233.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_233.Q1 to */SLICE_130.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[25]
CTOF_DEL    ---     0.238 */SLICE_130.C0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_232.CLK to */SLICE_232.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_232.Q1 to */SLICE_129.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[23]
CTOF_DEL    ---     0.238 */SLICE_129.C0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_147.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_147.A1 to */SLICE_147.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[13] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_145.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_145.A1 to */SLICE_145.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[9] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_156.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_156.B0 to */SLICE_156.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[6] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_153.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_153.B1 to */SLICE_153.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[1] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_146.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_146.A1 to */SLICE_146.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[11] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_142.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_142.A0 to */SLICE_142.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_157.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_157.B0 to */SLICE_157.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[8] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_325 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_325.C1 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_325.C1 to */SLICE_325.F1 mg5ahub/SLICE_325
ROUTE         1   e 0.001 */SLICE_325.F1 to *SLICE_325.DI1 mg5ahub/N_49_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_726 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_726.CLK to */SLICE_726.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_726 (from ipClk_c)
ROUTE         3   e 0.908 */SLICE_726.Q0 to */SLICE_163.B0 Test_reveal_coretop_instance/test_la0_inst_0/even_parity
CTOF_DEL    ---     0.238 */SLICE_163.B0 to */SLICE_163.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F0 to *SLICE_163.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_49_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_122.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_122.B0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_121.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_121.B1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_121.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_121.B0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_120.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_120.B1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_120.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_120.B0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_119.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_119.B1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_119.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_119.B0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_105.CLK to */SLICE_105.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_105.Q0 to */SLICE_163.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker
CTOF_DEL    ---     0.238 */SLICE_163.C0 to */SLICE_163.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163
ROUTE         1   e 0.001 */SLICE_163.F0 to *SLICE_163.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_49_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_139.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_139.A0 to */SLICE_139.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_138.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_138.B1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_137.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_137.B0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_136.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_136.B0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_137.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_137.B1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_136.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_136.B1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_135.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_135.B0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_132.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_132.B1 to */SLICE_132.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F1 to *SLICE_132.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_132.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_132.B0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_131.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_131.B1 to */SLICE_131.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F1 to *SLICE_131.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_131.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_131.B0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_130.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_130.B1 to */SLICE_130.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F1 to *SLICE_130.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_130.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_130.B0 to */SLICE_130.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130
ROUTE         1   e 0.001 */SLICE_130.F0 to *SLICE_130.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_129.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_129.B1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_129.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_129.B0 to */SLICE_129.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F0 to *SLICE_129.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_232.CLK to */SLICE_232.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_232.Q0 to */SLICE_128.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[22]
CTOF_DEL    ---     0.238 */SLICE_128.C1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_231.CLK to */SLICE_231.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_231.Q1 to */SLICE_128.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[21]
CTOF_DEL    ---     0.238 */SLICE_128.C0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_231.CLK to */SLICE_231.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_231.Q0 to */SLICE_127.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[20]
CTOF_DEL    ---     0.238 */SLICE_127.C1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_230.CLK to */SLICE_230.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_230.Q1 to */SLICE_127.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[19]
CTOF_DEL    ---     0.238 */SLICE_127.C0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_230.CLK to */SLICE_230.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_230.Q0 to */SLICE_126.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[18]
CTOF_DEL    ---     0.238 */SLICE_126.C1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_229.CLK to */SLICE_229.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_229.Q1 to */SLICE_126.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[17]
CTOF_DEL    ---     0.238 */SLICE_126.C0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_229.CLK to */SLICE_229.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_229.Q0 to */SLICE_125.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[16]
CTOF_DEL    ---     0.238 */SLICE_125.C1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_228.CLK to */SLICE_228.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_228.Q1 to */SLICE_125.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[15]
CTOF_DEL    ---     0.238 */SLICE_125.C0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_228.CLK to */SLICE_228.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_228.Q0 to */SLICE_124.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[14]
CTOF_DEL    ---     0.238 */SLICE_124.C1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_227.CLK to */SLICE_227.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_227.Q1 to */SLICE_124.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[13]
CTOF_DEL    ---     0.238 */SLICE_124.C0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_227.CLK to */SLICE_227.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_227.Q0 to */SLICE_123.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[12]
CTOF_DEL    ---     0.238 */SLICE_123.C1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_226.CLK to */SLICE_226.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_226.Q1 to */SLICE_123.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[11]
CTOF_DEL    ---     0.238 */SLICE_123.C0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_226.CLK to */SLICE_226.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_226.Q0 to */SLICE_122.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[10]
CTOF_DEL    ---     0.238 */SLICE_122.C1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_225.CLK to */SLICE_225.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_225.Q1 to */SLICE_122.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[9]
CTOF_DEL    ---     0.238 */SLICE_122.C0 to */SLICE_122.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F0 to *SLICE_122.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_225.CLK to */SLICE_225.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_225.Q0 to */SLICE_121.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[8]
CTOF_DEL    ---     0.238 */SLICE_121.C1 to */SLICE_121.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F1 to *SLICE_121.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q0 to */SLICE_274.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_274.C0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_224.CLK to */SLICE_224.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_224.Q0 to */SLICE_120.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[6]
CTOF_DEL    ---     0.238 */SLICE_120.C1 to */SLICE_120.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F1 to *SLICE_120.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_223.CLK to */SLICE_223.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_223.Q1 to */SLICE_120.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[5]
CTOF_DEL    ---     0.238 */SLICE_120.C0 to */SLICE_120.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120
ROUTE         1   e 0.001 */SLICE_120.F0 to *SLICE_120.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_223.CLK to */SLICE_223.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_223.Q0 to */SLICE_119.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[4]
CTOF_DEL    ---     0.238 */SLICE_119.C1 to */SLICE_119.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F1 to *SLICE_119.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_222.CLK to */SLICE_222.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_222.Q1 to */SLICE_119.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[3]
CTOF_DEL    ---     0.238 */SLICE_119.C0 to */SLICE_119.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119
ROUTE         1   e 0.001 */SLICE_119.F0 to *SLICE_119.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_222.CLK to */SLICE_222.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_222.Q0 to */SLICE_118.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[2]
CTOF_DEL    ---     0.238 */SLICE_118.C1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_221.CLK to */SLICE_221.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_221.Q1 to */SLICE_118.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[1]
CTOF_DEL    ---     0.238 */SLICE_118.C0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_142.CLK to */SLICE_142.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_142.Q1 to */SLICE_143.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]
CTOF_DEL    ---     0.238 */SLICE_143.B0 to */SLICE_143.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_146.CLK to */SLICE_146.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_146.Q1 to */SLICE_141.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]
CTOF_DEL    ---     0.238 */SLICE_141.B0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_152.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_152.A1 to */SLICE_152.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F1 to *SLICE_152.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_151.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_151.A1 to */SLICE_151.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F1 to *SLICE_151.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_150.A1 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_150.A1 to */SLICE_150.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F1 to *SLICE_150.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_160.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_160.B1 to */SLICE_160.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F1 to *SLICE_160.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[15] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_159.CLK to */SLICE_159.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_159.Q1 to */SLICE_160.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]
CTOF_DEL    ---     0.238 */SLICE_160.A0 to */SLICE_160.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[14] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to *u/SLICE_99.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2
CTOF_DEL    ---     0.238 *u/SLICE_99.A0 to *u/SLICE_99.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         1   e 0.001 *u/SLICE_99.F0 to */SLICE_99.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_242.CLK to */SLICE_242.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_242.Q0 to */SLICE_139.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[42]
CTOF_DEL    ---     0.238 */SLICE_139.C0 to */SLICE_139.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139
ROUTE         1   e 0.001 */SLICE_139.F0 to *SLICE_139.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_242.CLK to */SLICE_242.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_242.Q0 to */SLICE_138.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[42]
CTOF_DEL    ---     0.238 */SLICE_138.C1 to */SLICE_138.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F1 to *SLICE_138.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_240.CLK to */SLICE_240.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_240.Q1 to */SLICE_137.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[39]
CTOF_DEL    ---     0.238 */SLICE_137.C0 to */SLICE_137.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F0 to *SLICE_137.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_239.CLK to */SLICE_239.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_239.Q1 to */SLICE_136.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[37]
CTOF_DEL    ---     0.238 */SLICE_136.C0 to */SLICE_136.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F0 to *SLICE_136.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_241.CLK to */SLICE_241.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_241.Q0 to */SLICE_137.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[40]
CTOF_DEL    ---     0.238 */SLICE_137.C1 to */SLICE_137.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137
ROUTE         1   e 0.001 */SLICE_137.F1 to *SLICE_137.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_240.CLK to */SLICE_240.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_240.Q0 to */SLICE_136.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[38]
CTOF_DEL    ---     0.238 */SLICE_136.C1 to */SLICE_136.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136
ROUTE         1   e 0.001 */SLICE_136.F1 to *SLICE_136.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_238.CLK to */SLICE_238.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_238.Q1 to */SLICE_135.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[35]
CTOF_DEL    ---     0.238 */SLICE_135.C0 to */SLICE_135.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F0 to *SLICE_135.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_241.CLK to */SLICE_241.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_241.Q1 to */SLICE_138.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[41]
CTOF_DEL    ---     0.238 */SLICE_138.C0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_239.CLK to */SLICE_239.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_239.Q0 to */SLICE_135.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[36]
CTOF_DEL    ---     0.238 */SLICE_135.C1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_238.CLK to */SLICE_238.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_238.Q0 to */SLICE_134.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[34]
CTOF_DEL    ---     0.238 */SLICE_134.C1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_237.CLK to */SLICE_237.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_237.Q1 to */SLICE_134.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[33]
CTOF_DEL    ---     0.238 */SLICE_134.C0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_237.CLK to */SLICE_237.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_237.Q0 to */SLICE_133.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[32]
CTOF_DEL    ---     0.238 */SLICE_133.C1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_236.CLK to */SLICE_236.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_236.Q1 to */SLICE_133.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[31]
CTOF_DEL    ---     0.238 */SLICE_133.C0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_159.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_159.B1 to */SLICE_159.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[13] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_158.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_158.B1 to */SLICE_158.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[11] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_157.CLK to */SLICE_157.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_157.Q1 to */SLICE_158.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]
CTOF_DEL    ---     0.238 */SLICE_158.A0 to */SLICE_158.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[10] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_157.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_157.B1 to */SLICE_157.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[9] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_156.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_156.B1 to */SLICE_156.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[7] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_147.CLK to */SLICE_147.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_147.Q1 to */SLICE_148.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]
CTOF_DEL    ---     0.238 */SLICE_148.B0 to */SLICE_148.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[14] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_143.CLK to */SLICE_143.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_143.Q1 to */SLICE_144.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]
CTOF_DEL    ---     0.238 */SLICE_144.B0 to */SLICE_144.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[6] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_143.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_143.A1 to */SLICE_143.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[5] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_143.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_143.A0 to */SLICE_143.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F0 to *SLICE_143.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_141.CLK to */SLICE_141.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_141.Q1 to */SLICE_142.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]
CTOF_DEL    ---     0.238 */SLICE_142.B0 to */SLICE_142.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F0 to *SLICE_142.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_141.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_141.A1 to */SLICE_141.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[1] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_141.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_141.A0 to */SLICE_141.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F0 to *SLICE_141.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_152.A0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_152.A0 to */SLICE_152.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152
ROUTE         1   e 0.001 */SLICE_152.F0 to *SLICE_152.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_151.A0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_151.A0 to */SLICE_151.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151
ROUTE         1   e 0.001 */SLICE_151.F0 to *SLICE_151.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_150.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_150.A0 to */SLICE_150.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150
ROUTE         1   e 0.001 */SLICE_150.F0 to *SLICE_150.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_160.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_160.B0 to */SLICE_160.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F0 to *SLICE_160.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[14] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_158.CLK to */SLICE_158.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_158.Q1 to */SLICE_159.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]
CTOF_DEL    ---     0.238 */SLICE_159.A0 to */SLICE_159.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[12] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_158.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_158.B0 to */SLICE_158.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F0 to *SLICE_158.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[10] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_156.CLK to */SLICE_156.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_156.Q1 to */SLICE_157.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]
CTOF_DEL    ---     0.238 */SLICE_157.A0 to */SLICE_157.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F0 to *SLICE_157.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[8] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_154.CLK to */SLICE_154.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_154.Q1 to */SLICE_155.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]
CTOF_DEL    ---     0.238 */SLICE_155.A0 to */SLICE_155.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F0 to *SLICE_155.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_155.CLK to */SLICE_155.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_155.Q0 to */SLICE_153.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]
CTOF_DEL    ---     0.238 */SLICE_153.B0 to */SLICE_153.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_79.Q1 to */SLICE_191.A0 Test_reveal_coretop_instance/test_la0_inst_0/addr[15]
CTOF_DEL    ---     0.238 */SLICE_191.A0 to */SLICE_191.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191
ROUTE         2   e 0.001 */SLICE_191.F0 to *SLICE_191.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_191.Q0 to */SLICE_194.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.238 */SLICE_194.B1 to */SLICE_194.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194
ROUTE         1   e 0.001 */SLICE_194.F1 to *SLICE_194.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_191.Q0 to */SLICE_193.B1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.238 */SLICE_193.B1 to */SLICE_193.F1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F1 to *SLICE_193.DI1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_144.CLK to */SLICE_144.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_144.Q1 to */SLICE_145.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]
CTOF_DEL    ---     0.238 */SLICE_145.B0 to */SLICE_145.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[8] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_191.Q0 to */SLICE_193.B0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.238 */SLICE_193.B0 to */SLICE_193.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193
ROUTE         1   e 0.001 */SLICE_193.F0 to *SLICE_193.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_326 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q1 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_325.Q1 to */SLICE_326.C0 mg5ahub/bit_count_1
CTOF_DEL    ---     0.238 */SLICE_326.C0 to */SLICE_326.F0 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F0 to *SLICE_326.DI0 mg5ahub/N_48_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_145.CLK to */SLICE_145.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_145.Q1 to */SLICE_146.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]
CTOF_DEL    ---     0.238 */SLICE_146.B0 to */SLICE_146.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[10] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_326 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_326.B1 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_326.B1 to */SLICE_326.F1 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F1 to *SLICE_326.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_326 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q0 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_325.Q0 to */SLICE_326.D0 mg5ahub/bit_count_0
CTOF_DEL    ---     0.238 */SLICE_326.D0 to */SLICE_326.F0 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F0 to *SLICE_326.DI0 mg5ahub/N_48_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_148.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_148.A1 to */SLICE_148.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[15] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_148.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_148.A0 to */SLICE_148.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F0 to *SLICE_148.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[14] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_146.CLK to */SLICE_146.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_146.Q1 to */SLICE_147.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]
CTOF_DEL    ---     0.238 */SLICE_147.B0 to */SLICE_147.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[12] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_153.CLK to */SLICE_153.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_153.Q1 to */SLICE_154.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]
CTOF_DEL    ---     0.238 */SLICE_154.A0 to */SLICE_154.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_158.CLK to */SLICE_158.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_158.Q1 to */SLICE_153.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]
CTOF_DEL    ---     0.238 */SLICE_153.C0 to */SLICE_153.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F0 to *SLICE_153.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_162.C0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_162.C0 to */SLICE_162.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_191.Q0 to */SLICE_195.B0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd
CTOF_DEL    ---     0.238 */SLICE_195.B0 to */SLICE_195.F0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195
ROUTE         1   e 0.001 */SLICE_195.F0 to *SLICE_195.DI0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_224.CLK to */SLICE_224.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_224.Q1 to */SLICE_121.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[7]
CTOF_DEL    ---     0.238 */SLICE_121.C0 to */SLICE_121.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121
ROUTE         1   e 0.001 */SLICE_121.F0 to *SLICE_121.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to *u/SLICE_50.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 *u/SLICE_50.A0 to *u/SLICE_50.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F0 to */SLICE_50.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[1] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_521.CLK to */SLICE_521.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_521.Q0 to */SLICE_306.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_306.D0 to */SLICE_306.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306
ROUTE         1   e 0.001 */SLICE_306.F0 to *SLICE_306.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_end_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        10   e 0.908 *u/SLICE_96.Q0 to *u/SLICE_85.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1
CTOF_DEL    ---     0.238 *u/SLICE_85.C0 to *u/SLICE_85.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85
ROUTE         9   e 0.001 *u/SLICE_85.F0 to */SLICE_85.DI0 Test_reveal_coretop_instance/test_la0_inst_0/capture_dr (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q1 to */SLICE_306.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_306.A0 to */SLICE_306.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306
ROUTE         1   e 0.001 */SLICE_306.F0 to *SLICE_306.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_end_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_270 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_270.CLK to */SLICE_270.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_270 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_270.Q1 to */SLICE_262.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]
CTOF_DEL    ---     0.238 */SLICE_262.B1 to */SLICE_262.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F1 to *SLICE_262.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q0 to */SLICE_306.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_306.B0 to */SLICE_306.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306
ROUTE         1   e 0.001 */SLICE_306.F0 to *SLICE_306.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_end_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_268 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_268.CLK to */SLICE_268.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_268 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_268.Q1 to */SLICE_260.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]
CTOF_DEL    ---     0.238 */SLICE_260.B1 to */SLICE_260.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F1 to *SLICE_260.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.908 */SLICE_140.Q0 to *u/SLICE_90.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 *u/SLICE_90.C0 to *u/SLICE_90.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         2   e 0.001 *u/SLICE_90.F0 to */SLICE_90.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_266 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_266.CLK to */SLICE_266.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_266 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_266.Q1 to */SLICE_258.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]
CTOF_DEL    ---     0.238 */SLICE_258.B1 to */SLICE_258.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F1 to *SLICE_258.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_93.Q0 to *u/SLICE_99.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2
CTOF_DEL    ---     0.238 *u/SLICE_99.C0 to *u/SLICE_99.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         1   e 0.001 *u/SLICE_99.F0 to */SLICE_99.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_264 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_264.CLK to */SLICE_264.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_264 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_264.Q1 to */SLICE_256.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]
CTOF_DEL    ---     0.238 */SLICE_256.B1 to */SLICE_256.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F1 to *SLICE_256.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_276.Q1 to */SLICE_274.D0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_274.D0 to */SLICE_274.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274
ROUTE         1   e 0.001 */SLICE_274.F0 to *SLICE_274.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_144.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_144.A0 to */SLICE_144.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F0 to *SLICE_144.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[6] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to *u/SLICE_99.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 *u/SLICE_99.B0 to *u/SLICE_99.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99
ROUTE         1   e 0.001 *u/SLICE_99.F0 to */SLICE_99.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_155.CLK to */SLICE_155.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_155.Q1 to */SLICE_156.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]
CTOF_DEL    ---     0.238 */SLICE_156.A0 to */SLICE_156.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F0 to *SLICE_156.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[6] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_138.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_138.B0 to */SLICE_138.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138
ROUTE         1   e 0.001 */SLICE_138.F0 to *SLICE_138.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_270 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_270.CLK to */SLICE_270.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_270 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_270.Q0 to */SLICE_262.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]
CTOF_DEL    ---     0.238 */SLICE_262.B0 to */SLICE_262.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262
ROUTE         1   e 0.001 */SLICE_262.F0 to *SLICE_262.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_135.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_135.B1 to */SLICE_135.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135
ROUTE         1   e 0.001 */SLICE_135.F1 to *SLICE_135.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_268 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_268.CLK to */SLICE_268.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_268 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_268.Q0 to */SLICE_260.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]
CTOF_DEL    ---     0.238 */SLICE_260.B0 to */SLICE_260.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260
ROUTE         1   e 0.001 */SLICE_260.F0 to *SLICE_260.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_134.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_134.B1 to */SLICE_134.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F1 to *SLICE_134.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_266 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_266.CLK to */SLICE_266.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_266 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_266.Q0 to */SLICE_258.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]
CTOF_DEL    ---     0.238 */SLICE_258.B0 to */SLICE_258.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258
ROUTE         1   e 0.001 */SLICE_258.F0 to *SLICE_258.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_134.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_134.B0 to */SLICE_134.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134
ROUTE         1   e 0.001 */SLICE_134.F0 to *SLICE_134.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   Clockdomain-Transfer "ipClk_c" TO "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_264 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_264.CLK to */SLICE_264.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_264 (from ipClk_c)
ROUTE         1   e 0.908 */SLICE_264.Q0 to */SLICE_256.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]
CTOF_DEL    ---     0.238 */SLICE_256.B0 to */SLICE_256.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256
ROUTE         1   e 0.001 */SLICE_256.F0 to *SLICE_256.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_133.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_133.B1 to */SLICE_133.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F1 to *SLICE_133.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_235.CLK to */SLICE_235.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_235.Q1 to */SLICE_132.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[29]
CTOF_DEL    ---     0.238 */SLICE_132.C0 to */SLICE_132.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132
ROUTE         1   e 0.001 */SLICE_132.F0 to *SLICE_132.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_96.CLK to *u/SLICE_96.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (from jtaghub16_jtck)
ROUTE        25   e 0.908 *u/SLICE_96.Q1 to */SLICE_133.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2
CTOF_DEL    ---     0.238 */SLICE_133.B0 to */SLICE_133.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133
ROUTE         1   e 0.001 */SLICE_133.F0 to *SLICE_133.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_234.CLK to */SLICE_234.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_234.Q1 to */SLICE_131.C0 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[27]
CTOF_DEL    ---     0.238 */SLICE_131.C0 to */SLICE_131.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131
ROUTE         1   e 0.001 */SLICE_131.F0 to *SLICE_131.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_108.CLK to */SLICE_108.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_108.Q0 to *u/SLICE_75.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]
CTOF_DEL    ---     0.238 *u/SLICE_75.D0 to *u/SLICE_75.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75
ROUTE         1   e 0.001 *u/SLICE_75.F0 to */SLICE_75.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_43_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_155.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_155.B1 to */SLICE_155.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[5] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_128.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_128.B1 to */SLICE_128.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F1 to *SLICE_128.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_154.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_154.B1 to */SLICE_154.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[3] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_128.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_128.B0 to */SLICE_128.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128
ROUTE         1   e 0.001 */SLICE_128.F0 to *SLICE_128.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_233.CLK to */SLICE_233.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_233.Q0 to */SLICE_129.C1 Test_reveal_coretop_instance/test_la0_inst_0/trace_dout[24]
CTOF_DEL    ---     0.238 */SLICE_129.C1 to */SLICE_129.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129
ROUTE         1   e 0.001 */SLICE_129.F1 to *SLICE_129.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_127.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_127.B1 to */SLICE_127.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F1 to *SLICE_127.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_118.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_118.B0 to */SLICE_118.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F0 to *SLICE_118.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_127.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_127.B0 to */SLICE_127.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127
ROUTE         1   e 0.001 */SLICE_127.F0 to *SLICE_127.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_147.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_147.A0 to */SLICE_147.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F0 to *SLICE_147.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[12] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_126.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_126.B1 to */SLICE_126.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F1 to *SLICE_126.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_145.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_145.A0 to */SLICE_145.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F0 to *SLICE_145.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[8] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_95.CLK to *u/SLICE_95.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_95.Q0 to */SLICE_126.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0
CTOF_DEL    ---     0.238 */SLICE_126.B0 to */SLICE_126.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126
ROUTE         1   e 0.001 */SLICE_126.F0 to *SLICE_126.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_154.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_154.B0 to */SLICE_154.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F0 to *SLICE_154.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[2] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_125.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_125.B1 to */SLICE_125.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F1 to *SLICE_125.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_325 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_325.C0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_325.C0 to */SLICE_325.F0 mg5ahub/SLICE_325
ROUTE         1   e 0.001 */SLICE_325.F0 to *SLICE_325.DI0 mg5ahub/bit_count_3_iv_0_m4_0 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_125.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_125.B0 to */SLICE_125.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125
ROUTE         1   e 0.001 */SLICE_125.F0 to *SLICE_125.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_555.CLK to */SLICE_555.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_555.Q0 to */SLICE_146.A0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1
CTOF_DEL    ---     0.238 */SLICE_146.A0 to */SLICE_146.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F0 to *SLICE_146.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[10] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_124.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_124.B1 to */SLICE_124.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F1 to *SLICE_124.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.908 */SLICE_161.Q0 to */SLICE_159.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_159.B0 to */SLICE_159.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F0 to *SLICE_159.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[12] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_124.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_124.B0 to */SLICE_124.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124
ROUTE         1   e 0.001 */SLICE_124.F0 to *SLICE_124.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay mg5ahub/SLICE_342 to mg5ahub/SLICE_326 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_342.CLK to */SLICE_342.Q0 mg5ahub/SLICE_342 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_342.Q0 to */SLICE_326.A0 mg5ahub/jshift_d1
CTOF_DEL    ---     0.238 */SLICE_326.A0 to */SLICE_326.F0 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F0 to *SLICE_326.DI0 mg5ahub/N_48_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_123.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_123.B1 to */SLICE_123.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F1 to *SLICE_123.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83 (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_525.CLK to */SLICE_525.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_525.Q0 to */SLICE_287.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2
CTOF_DEL    ---     0.238 */SLICE_287.A0 to */SLICE_287.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_i (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_123.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_123.B0 to */SLICE_123.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123
ROUTE         1   e 0.001 */SLICE_123.F0 to *SLICE_123.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_97.CLK to *u/SLICE_97.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_97.Q0 to */SLICE_122.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0
CTOF_DEL    ---     0.238 */SLICE_122.B1 to */SLICE_122.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122
ROUTE         1   e 0.001 */SLICE_122.F1 to *SLICE_122.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.587ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118 (1.510ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_98.CLK to *u/SLICE_98.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (from jtaghub16_jtck)
ROUTE         9   e 0.908 *u/SLICE_98.Q0 to */SLICE_118.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0
CTOF_DEL    ---     0.238 */SLICE_118.B1 to */SLICE_118.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118
ROUTE         1   e 0.001 */SLICE_118.F1 to *SLICE_118.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1] (to jtaghub16_jtck)
                  --------
                    1.510   (39.8% logic, 60.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.555ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.478ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.478   (84.0% logic, 16.0% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.555ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.478ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.478   (84.0% logic, 16.0% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.555ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.478ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.478   (84.0% logic, 16.0% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.555ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.478ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF1_DE  ---     0.310 */SLICE_39.FCI to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    1.478   (84.0% logic, 16.0% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.553ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.476ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.476   (83.9% logic, 16.1% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.553ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.476ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.476   (83.9% logic, 16.1% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.553ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.476ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.476   (83.9% logic, 16.1% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.553ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.476ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.476   (83.9% logic, 16.1% route), 7 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_41.FCI to *1/SLICE_41.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F1 to */SLICE_41.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
C0TOFCO_DE  ---     0.550 *1/SLICE_39.A0 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q0 to *1/SLICE_38.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
C0TOFCO_DE  ---     0.550 *1/SLICE_38.A0 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q0 to *1/SLICE_37.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
C0TOFCO_DE  ---     0.550 *1/SLICE_37.A0 to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_67 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q0 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q0 to *b/SLICE_68.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.550 *b/SLICE_68.C0 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF1_DE  ---     0.310 */SLICE_67.FCI to *b/SLICE_67.F1 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F1 to */SLICE_67.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_50.Q0 to *u/SLICE_50.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]
C0TOFCO_DE  ---     0.550 *u/SLICE_50.B0 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_49.FCI to *u/SLICE_49.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F1 to */SLICE_49.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_66 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q0 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_67.Q0 to *b/SLICE_67.C0 mg5ahub/rom_rd_addr_3
C0TOFCO_DE  ---     0.550 *b/SLICE_67.C0 to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.310 */SLICE_66.FCI to *b/SLICE_66.F1 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F1 to */SLICE_66.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF1_DE  ---     0.310 */SLICE_39.FCI to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.534ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.457ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF1_DE  ---     0.310 */SLICE_40.FCI to *1/SLICE_40.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F1 to */SLICE_40.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6] (to jtaghub16_jtck)
                  --------
                    1.457   (83.9% logic, 16.1% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_66 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q0 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q0 to *b/SLICE_68.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.550 *b/SLICE_68.C0 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.240 */SLICE_66.FCI to *b/SLICE_66.F0 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F0 to */SLICE_66.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
C0TOFCO_DE  ---     0.550 *1/SLICE_39.A0 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q0 to *1/SLICE_38.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
C0TOFCO_DE  ---     0.550 *1/SLICE_38.A0 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF0_DE  ---     0.240 */SLICE_39.FCI to *1/SLICE_39.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F0 to */SLICE_39.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7] (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_50.Q0 to *u/SLICE_50.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]
C0TOFCO_DE  ---     0.550 *u/SLICE_50.B0 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_49.FCI to */SLICE_49.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_48.FCI to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_65 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q0 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_67.Q0 to *b/SLICE_67.C0 mg5ahub/rom_rd_addr_3
C0TOFCO_DE  ---     0.550 *b/SLICE_67.C0 to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.067 */SLICE_66.FCI to */SLICE_66.FCO mg5ahub/SLICE_66
ROUTE         1   e 0.001 */SLICE_66.FCO to */SLICE_65.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.240 */SLICE_65.FCI to *b/SLICE_65.F0 mg5ahub/SLICE_65
ROUTE         1   e 0.001 *b/SLICE_65.F0 to */SLICE_65.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_40.FCI to *1/SLICE_40.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F0 to */SLICE_40.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.532ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.455ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q0 to *1/SLICE_37.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
C0TOFCO_DE  ---     0.550 *1/SLICE_37.A0 to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.455   (83.8% logic, 16.2% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_312.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_85.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_572 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_572.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_718.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_86 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_86.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_93.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_91.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_95 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_95.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_96 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_96.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_314.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_97 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_97.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_101 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_101.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_98 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_98.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_555.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_111.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_99.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_105.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_310.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_140.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_161.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_308.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_162.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to *u/SLICE_75.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_311.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_307.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_313.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_309.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_104.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_100.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.497ns delay SLICE_522 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (1.271ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363  SLICE_522.CLK to   SLICE_522.Q0 SLICE_522 (from jtaghub16_jtck)
ROUTE        63   e 0.908   SLICE_522.Q0 to */SLICE_163.CE jtaghub16_ip_enable0 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.487ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.410ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q1 to *1/SLICE_39.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
C1TOFCO_DE  ---     0.367 *1/SLICE_39.A1 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.410   (83.3% logic, 16.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.487ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.410ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.410   (83.3% logic, 16.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.487ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.410ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.410   (83.3% logic, 16.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.487ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.410ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF1_DE  ---     0.310 */SLICE_39.FCI to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    1.410   (83.3% logic, 16.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.487ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.410ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF1_DE  ---     0.310 */SLICE_40.FCI to *1/SLICE_40.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F1 to */SLICE_40.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6] (to jtaghub16_jtck)
                  --------
                    1.410   (83.3% logic, 16.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.487ns delay mg5ahub/SLICE_64 to mg5ahub/SLICE_66 (1.410ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_64.CLK to *b/SLICE_64.Q1 mg5ahub/SLICE_64 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_64.Q1 to *b/SLICE_64.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.367 *b/SLICE_64.C1 to */SLICE_64.FCO mg5ahub/SLICE_64
ROUTE         1   e 0.001 */SLICE_64.FCO to */SLICE_68.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.067 */SLICE_68.FCI to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.310 */SLICE_66.FCI to *b/SLICE_66.F1 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F1 to */SLICE_66.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.410   (83.3% logic, 16.7% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.485ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.408ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF0_DE  ---     0.240 */SLICE_39.FCI to *1/SLICE_39.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F0 to */SLICE_39.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7] (to jtaghub16_jtck)
                  --------
                    1.408   (83.2% logic, 16.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.485ns delay mg5ahub/SLICE_64 to mg5ahub/SLICE_65 (1.408ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_64.CLK to *b/SLICE_64.Q1 mg5ahub/SLICE_64 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_64.Q1 to *b/SLICE_64.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.367 *b/SLICE_64.C1 to */SLICE_64.FCO mg5ahub/SLICE_64
ROUTE         1   e 0.001 */SLICE_64.FCO to */SLICE_68.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.067 */SLICE_68.FCI to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.067 */SLICE_66.FCI to */SLICE_66.FCO mg5ahub/SLICE_66
ROUTE         1   e 0.001 */SLICE_66.FCO to */SLICE_65.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.240 */SLICE_65.FCI to *b/SLICE_65.F0 mg5ahub/SLICE_65
ROUTE         1   e 0.001 *b/SLICE_65.F0 to */SLICE_65.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.408   (83.2% logic, 16.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.485ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.408ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q1 to *1/SLICE_39.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
C1TOFCO_DE  ---     0.367 *1/SLICE_39.A1 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.408   (83.2% logic, 16.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.485ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.408ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.408   (83.2% logic, 16.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.485ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.408ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.408   (83.2% logic, 16.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.485ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.408ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.408   (83.2% logic, 16.8% route), 6 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO18 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO18 to */SLICE_221.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[0] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_1_0.CLKR to *a7_0_1_0.DO21 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_1_0.DO21 to */SLICE_240.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[39] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_1_0.CLKR to *a7_0_1_0.DO19 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_1_0.DO19 to */SLICE_239.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[37] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO17 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO17 to */SLICE_238.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[35] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO15 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO15 to */SLICE_237.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[33] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO13 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO13 to */SLICE_236.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[31] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO11 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO11 to */SLICE_235.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[29] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO9 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO9 to */SLICE_234.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[27] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO7 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO7 to */SLICE_233.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[25] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO5 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO5 to */SLICE_232.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[23] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO3 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO3 to */SLICE_231.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[21] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO1 to */SLICE_230.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[19] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO35 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO35 to */SLICE_229.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[17] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO33 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO33 to */SLICE_228.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[15] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO31 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO31 to */SLICE_227.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[13] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO29 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO29 to */SLICE_226.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[11] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO27 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO27 to */SLICE_225.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[9] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO25 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO25 to */SLICE_224.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[7] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO23 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO23 to */SLICE_223.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[5] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO21 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO21 to */SLICE_222.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[3] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_1_0.CLKR to *a7_0_1_0.DO23 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_1_0.DO23 to */SLICE_241.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[41] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_242 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_1_0.CLKR to *a7_0_1_0.DO24 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_1_0.DO24 to */SLICE_242.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[42] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_241 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_1_0.CLKR to *a7_0_1_0.DO22 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_1_0.DO22 to */SLICE_241.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[40] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_240 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_1_0.CLKR to *a7_0_1_0.DO20 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_1_0.DO20 to */SLICE_240.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[38] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_239 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_1_0.CLKR to *a7_0_1_0.DO18 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_1_0.DO18 to */SLICE_239.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[36] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_238 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO16 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO16 to */SLICE_238.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[34] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_237 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO14 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO14 to */SLICE_237.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[32] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_236 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO12 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO12 to */SLICE_236.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[30] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_235 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO10 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO10 to */SLICE_235.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[28] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_234 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO8 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO8 to */SLICE_234.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[26] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_233 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO6 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO6 to */SLICE_233.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[24] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_232 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO4 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO4 to */SLICE_232.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[22] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_231 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO2 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO2 to */SLICE_231.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[20] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_229 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO34 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO34 to */SLICE_229.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[16] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_228 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO32 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO32 to */SLICE_228.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[14] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_227 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO30 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO30 to */SLICE_227.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[12] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_226 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO28 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO28 to */SLICE_226.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[10] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_225 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO26 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO26 to */SLICE_225.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[8] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_224 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO24 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO24 to */SLICE_224.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[6] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_223 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO22 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO22 to */SLICE_223.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[4] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_222 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO20 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO20 to */SLICE_222.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[2] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_221 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *a7_0_0_1.DO19 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *a7_0_0_1.DO19 to */SLICE_221.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[1] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.467ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_230 (1.316ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
C2Q_DEL     ---     0.408 *a7_0_0_1.CLKR to *ca7_0_0_1.DO0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (from jtaghub16_jtck)
ROUTE         1   e 0.908 *ca7_0_0_1.DO0 to */SLICE_230.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[18] (to jtaghub16_jtck)
                  --------
                    1.316   (31.0% logic, 69.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_66 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q0 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_67.Q0 to *b/SLICE_67.C0 mg5ahub/rom_rd_addr_3
C0TOFCO_DE  ---     0.550 *b/SLICE_67.C0 to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.240 */SLICE_66.FCI to *b/SLICE_66.F0 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F0 to */SLICE_66.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
C0TOFCO_DE  ---     0.550 *1/SLICE_39.A0 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
C0TOFCO_DE  ---     0.550 *1/SLICE_41.A0 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_40.FCI to *1/SLICE_40.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F0 to */SLICE_40.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_36.Q0 to *1/SLICE_36.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
C0TOFCO_DE  ---     0.550 *1/SLICE_36.A0 to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q0 to *1/SLICE_38.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
C0TOFCO_DE  ---     0.550 *1/SLICE_38.A0 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q0 to *1/SLICE_37.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
C0TOFCO_DE  ---     0.550 *1/SLICE_37.A0 to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_50.Q0 to *u/SLICE_50.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]
C0TOFCO_DE  ---     0.550 *u/SLICE_50.B0 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_49.FCI to *u/SLICE_49.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F0 to */SLICE_49.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_49.Q0 to *u/SLICE_49.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]
C0TOFCO_DE  ---     0.550 *u/SLICE_49.B0 to */SLICE_49.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_48.FCI to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_67 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q0 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q0 to *b/SLICE_68.C0 mg5ahub/rom_rd_addr_1
C0TOFCO_DE  ---     0.550 *b/SLICE_68.C0 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF0_DE  ---     0.240 */SLICE_67.FCI to *b/SLICE_67.F0 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F0 to */SLICE_67.DI0 mg5ahub/rom_rd_addr_s_3 (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay mg5ahub/SLICE_66 to mg5ahub/SLICE_65 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_66.CLK to *b/SLICE_66.Q0 mg5ahub/SLICE_66 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_66.Q0 to *b/SLICE_66.C0 mg5ahub/rom_rd_addr_5
C0TOFCO_DE  ---     0.550 *b/SLICE_66.C0 to */SLICE_66.FCO mg5ahub/SLICE_66
ROUTE         1   e 0.001 */SLICE_66.FCO to */SLICE_65.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.240 */SLICE_65.FCI to *b/SLICE_65.F0 mg5ahub/SLICE_65
ROUTE         1   e 0.001 *b/SLICE_65.F0 to */SLICE_65.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
C0TOFCO_DE  ---     0.550 *1/SLICE_42.A0 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_41.FCI to *1/SLICE_41.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F0 to */SLICE_41.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.464ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.387ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
C0TOFCO_DE  ---     0.550 *1/SLICE_40.A0 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF0_DE  ---     0.240 */SLICE_39.FCI to *1/SLICE_39.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F0 to */SLICE_39.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7] (to jtaghub16_jtck)
                  --------
                    1.387   (83.1% logic, 16.9% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_329 to SLICE_522 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_329.CLK to */SLICE_329.Q1 mg5ahub/SLICE_329 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_329.Q1 to   SLICE_522.M0 mg5ahub/er1_shift_reg_4 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_337 to mg5ahub/SLICE_336 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_337.CLK to */SLICE_337.Q0 mg5ahub/SLICE_337 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_337.Q0 to */SLICE_336.M1 mg5ahub/er1_shift_reg_19 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_551 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_551.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_111.CLK to */SLICE_111.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_111.Q0 to */SLICE_628.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_109.M1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_91.Q1 to */SLICE_718.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_101 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_100.CLK to */SLICE_100.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_100.Q1 to */SLICE_101.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_109.CLK to */SLICE_109.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_109.Q0 to *u/SLICE_79.M1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_602.CLK to */SLICE_602.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (from jtaghub16_jtck)
ROUTE        21   e 0.908 */SLICE_602.Q0 to *u/SLICE_73.M1 Test_reveal_coretop_instance/test_la0_inst_0/addr[4] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_79.Q0 to */SLICE_116.M1 Test_reveal_coretop_instance/test_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_191.CLK to */SLICE_191.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191 (from jtaghub16_jtck)
ROUTE         7   e 0.908 */SLICE_191.Q0 to */SLICE_192.M0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_117.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_116 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_116.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_315 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        55   e 0.908 *u/SLICE_72.Q0 to */SLICE_315.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[0] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_79.Q0 to *u/SLICE_78.M1 Test_reveal_coretop_instance/test_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        34   e 0.908 *u/SLICE_73.Q0 to *u/SLICE_72.M1 Test_reveal_coretop_instance/test_la0_inst_0/addr[2] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         5   e 0.908 *u/SLICE_79.Q1 to */SLICE_592.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[15] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_538.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_86 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_85.CLK to *u/SLICE_85.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *u/SLICE_85.Q1 to *u/SLICE_86.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_525.M0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_592.CLK to */SLICE_592.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592 (from jtaghub16_jtck)
ROUTE        26   e 0.908 */SLICE_592.Q0 to */SLICE_555.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr_15 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_86 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_87 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_86.CLK to *u/SLICE_86.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_86 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *u/SLICE_86.Q0 to *u/SLICE_87.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_99.CLK to *u/SLICE_99.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE         2   e 0.908 *u/SLICE_99.Q1 to */SLICE_100.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_615 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_163.CLK to */SLICE_163.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163 (from jtaghub16_jtck)
ROUTE         4   e 0.908 */SLICE_163.Q0 to */SLICE_615.M0 Test_reveal_coretop_instance/test_la0_inst_0/parity_err (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_331 to mg5ahub/SLICE_340 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_331.CLK to */SLICE_331.Q0 mg5ahub/SLICE_331 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_331.Q0 to */SLICE_340.M0 mg5ahub/er1_shift_reg_7 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/SLICE_521 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.908 *u/SLICE_93.Q1 to */SLICE_521.M0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 to Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_75.CLK to *u/SLICE_75.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_75.Q0 to */SLICE_602.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[5] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_337 to mg5ahub/SLICE_467 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_337.CLK to */SLICE_337.Q1 mg5ahub/SLICE_337 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_337.Q1 to */SLICE_467.M0 mg5ahub/er1_shift_reg_20 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_330 to mg5ahub/SLICE_329 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_330.CLK to */SLICE_330.Q0 mg5ahub/SLICE_330 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_330.Q0 to */SLICE_329.M1 mg5ahub/er1_shift_reg_5 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_330 to mg5ahub/SLICE_339 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_330.CLK to */SLICE_330.Q1 mg5ahub/SLICE_330 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_330.Q1 to */SLICE_339.M1 mg5ahub/er1_shift_reg_6 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_332 to mg5ahub/SLICE_331 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_332.CLK to */SLICE_332.Q0 mg5ahub/SLICE_332 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_332.Q0 to */SLICE_331.M1 mg5ahub/er1_shift_reg_9 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_334 to mg5ahub/SLICE_333 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_334.CLK to */SLICE_334.Q0 mg5ahub/SLICE_334 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_334.Q0 to */SLICE_333.M1 mg5ahub/er1_shift_reg_13 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_333 to mg5ahub/SLICE_332 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_333.CLK to */SLICE_333.Q0 mg5ahub/SLICE_333 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_333.Q0 to */SLICE_332.M1 mg5ahub/er1_shift_reg_11 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_335 to mg5ahub/SLICE_334 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_335.CLK to */SLICE_335.Q0 mg5ahub/SLICE_335 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_335.Q0 to */SLICE_334.M1 mg5ahub/er1_shift_reg_15 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_336 to mg5ahub/SLICE_335 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_336.CLK to */SLICE_336.Q0 mg5ahub/SLICE_336 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_336.Q0 to */SLICE_335.M1 mg5ahub/er1_shift_reg_17 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_329 to mg5ahub/SLICE_328 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_329.CLK to */SLICE_329.Q0 mg5ahub/SLICE_329 (from jtaghub16_jtck)
ROUTE         1   e 0.908 */SLICE_329.Q0 to */SLICE_328.M1 mg5ahub/er1_shift_reg_3 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        19   e 0.908 *u/SLICE_76.Q0 to */SLICE_108.M1 Test_reveal_coretop_instance/test_la0_inst_0/addr[8] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_330 to mg5ahub/SLICE_339 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_330.CLK to */SLICE_330.Q0 mg5ahub/SLICE_330 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_330.Q0 to */SLICE_339.M0 mg5ahub/er1_shift_reg_5 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_568 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.908 *u/SLICE_78.Q1 to */SLICE_568.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_331 to mg5ahub/SLICE_330 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_331.CLK to */SLICE_331.Q0 mg5ahub/SLICE_331 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_331.Q0 to */SLICE_330.M1 mg5ahub/er1_shift_reg_7 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_77.Q0 to *u/SLICE_76.M1 Test_reveal_coretop_instance/test_la0_inst_0/addr[10] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_638 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_628.CLK to */SLICE_628.Q0 Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628 (from jtaghub16_jtck)
ROUTE         6   e 0.908 */SLICE_628.Q0 to */SLICE_638.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_639 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_79.Q0 to */SLICE_639.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_547 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_79.Q0 to */SLICE_547.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        18   e 0.908 *u/SLICE_78.Q0 to *u/SLICE_77.M1 Test_reveal_coretop_instance/test_la0_inst_0/addr[12] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_117 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         6   e 0.908 *u/SLICE_79.Q0 to */SLICE_117.M1 Test_reveal_coretop_instance/test_la0_inst_0/addr[14] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.422ns delay mg5ahub/SLICE_331 to mg5ahub/SLICE_340 (1.271ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_331.CLK to */SLICE_331.Q1 mg5ahub/SLICE_331 (from jtaghub16_jtck)
ROUTE         2   e 0.908 */SLICE_331.Q1 to */SLICE_340.M1 mg5ahub/er1_shift_reg_8 (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q1 to *1/SLICE_39.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
C1TOFCO_DE  ---     0.367 *1/SLICE_39.A1 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q1 to *1/SLICE_38.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
C1TOFCO_DE  ---     0.367 *1/SLICE_38.A1 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF1_DE  ---     0.310 */SLICE_40.FCI to *1/SLICE_40.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F1 to */SLICE_40.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6] (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_51.CLK to *u/SLICE_51.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_51.Q1 to *u/SLICE_51.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_51.B1 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_50.FCI to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_49.FCI to *u/SLICE_49.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F1 to */SLICE_49.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF1_DE  ---     0.310 */SLICE_39.FCI to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_41.FCI to *1/SLICE_41.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F1 to */SLICE_41.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay mg5ahub/SLICE_64 to mg5ahub/SLICE_67 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_64.CLK to *b/SLICE_64.Q1 mg5ahub/SLICE_64 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_64.Q1 to *b/SLICE_64.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.367 *b/SLICE_64.C1 to */SLICE_64.FCO mg5ahub/SLICE_64
ROUTE         1   e 0.001 */SLICE_64.FCO to */SLICE_68.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.067 */SLICE_68.FCI to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF1_DE  ---     0.310 */SLICE_67.FCI to *b/SLICE_67.F1 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F1 to */SLICE_67.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.419ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_66 (1.342ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q1 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q1 to *b/SLICE_68.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.367 *b/SLICE_68.C1 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.310 */SLICE_66.FCI to *b/SLICE_66.F1 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F1 to */SLICE_66.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.342   (82.5% logic, 17.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay mg5ahub/SLICE_64 to mg5ahub/SLICE_66 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_64.CLK to *b/SLICE_64.Q1 mg5ahub/SLICE_64 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_64.Q1 to *b/SLICE_64.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.367 *b/SLICE_64.C1 to */SLICE_64.FCO mg5ahub/SLICE_64
ROUTE         1   e 0.001 */SLICE_64.FCO to */SLICE_68.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.067 */SLICE_68.FCI to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.240 */SLICE_66.FCI to *b/SLICE_66.F0 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F0 to */SLICE_66.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q1 to *1/SLICE_38.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
C1TOFCO_DE  ---     0.367 *1/SLICE_38.A1 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_65 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q1 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q1 to *b/SLICE_68.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.367 *b/SLICE_68.C1 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.067 */SLICE_66.FCI to */SLICE_66.FCO mg5ahub/SLICE_66
ROUTE         1   e 0.001 */SLICE_66.FCO to */SLICE_65.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.240 */SLICE_65.FCI to *b/SLICE_65.F0 mg5ahub/SLICE_65
ROUTE         1   e 0.001 *b/SLICE_65.F0 to */SLICE_65.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_51.CLK to *u/SLICE_51.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_51.Q1 to *u/SLICE_51.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_51.B1 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_50.FCI to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_49.FCI to */SLICE_49.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_48.FCI to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_40.FCI to *1/SLICE_40.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F0 to */SLICE_40.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF0_DE  ---     0.240 */SLICE_39.FCI to *1/SLICE_39.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F0 to */SLICE_39.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7] (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.417ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.340ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q1 to *1/SLICE_39.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
C1TOFCO_DE  ---     0.367 *1/SLICE_39.A1 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.340   (82.4% logic, 17.6% route), 5 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.381ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (1.304ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_314.CLK to */SLICE_314.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_314.Q0 to */SLICE_314.C1 Test_reveal_coretop_instance/test_la0_inst_0/wr_din[14]
CTOF_DEL    ---     0.238 */SLICE_314.C1 to */SLICE_314.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.232 */SLICE_314.F1 to */SLICE_314.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_14_i_0[14]
CTOF_DEL    ---     0.238 */SLICE_314.C0 to */SLICE_314.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314
ROUTE         1   e 0.001 */SLICE_314.F0 to *SLICE_314.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i (to jtaghub16_jtck)
                  --------
                    1.304   (64.3% logic, 35.7% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.381ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (1.304ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_140.CLK to */SLICE_140.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140 (from jtaghub16_jtck)
ROUTE         5   e 0.232 */SLICE_140.Q0 to */SLICE_140.C1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block
CTOF_DEL    ---     0.238 */SLICE_140.C1 to */SLICE_140.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.232 */SLICE_140.F1 to */SLICE_140.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block_3_iv_i_a2_0_3
CTOF_DEL    ---     0.238 */SLICE_140.C0 to */SLICE_140.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140
ROUTE         1   e 0.001 */SLICE_140.F0 to *SLICE_140.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36 (to jtaghub16_jtck)
                  --------
                    1.304   (64.3% logic, 35.7% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay mg5ahub/SLICE_64 to mg5ahub/SLICE_68 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_64.CLK to *b/SLICE_64.Q1 mg5ahub/SLICE_64 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_64.Q1 to *b/SLICE_64.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.367 *b/SLICE_64.C1 to */SLICE_64.FCO mg5ahub/SLICE_64
ROUTE         1   e 0.001 */SLICE_64.FCO to */SLICE_68.FCI mg5ahub/rom_rd_addr_cry_0
FCITOF1_DE  ---     0.310 */SLICE_68.FCI to *b/SLICE_68.F1 mg5ahub/SLICE_68
ROUTE         1   e 0.001 *b/SLICE_68.F1 to */SLICE_68.DI1 mg5ahub/rom_rd_addr_s_2 (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF1_DE  ---     0.310 */SLICE_39.FCI to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_41.FCI to *1/SLICE_41.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F1 to */SLICE_41.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_66 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q1 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_67.Q1 to *b/SLICE_67.C1 mg5ahub/rom_rd_addr_4
C1TOFCO_DE  ---     0.367 *b/SLICE_67.C1 to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF1_DE  ---     0.310 */SLICE_66.FCI to *b/SLICE_66.F1 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F1 to */SLICE_66.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q1 to *1/SLICE_38.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
C1TOFCO_DE  ---     0.367 *1/SLICE_38.A1 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF1_DE  ---     0.310 */SLICE_37.FCI to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF1_DE  ---     0.310 */SLICE_40.FCI to *1/SLICE_40.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F1 to */SLICE_40.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_51.CLK to *u/SLICE_51.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_51.Q1 to *u/SLICE_51.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_51.B1 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOF1_DE  ---     0.310 */SLICE_50.FCI to *u/SLICE_50.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F1 to */SLICE_50.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_50.Q1 to *u/SLICE_50.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]
C1TOFCO_DE  ---     0.367 *u/SLICE_50.B1 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF1_DE  ---     0.310 */SLICE_49.FCI to *u/SLICE_49.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F1 to */SLICE_49.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_67 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q1 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q1 to *b/SLICE_68.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.367 *b/SLICE_68.C1 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF1_DE  ---     0.310 */SLICE_67.FCI to *b/SLICE_67.F1 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F1 to */SLICE_67.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q1 to *1/SLICE_37.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
C1TOFCO_DE  ---     0.367 *1/SLICE_37.A1 to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF1_DE  ---     0.310 */SLICE_36.FCI to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q1 to *1/SLICE_39.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
C1TOFCO_DE  ---     0.367 *1/SLICE_39.A1 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF1_DE  ---     0.310 */SLICE_38.FCI to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.351ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (1.274ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOF1_DE  ---     0.310 */SLICE_42.FCI to *1/SLICE_42.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 *1/SLICE_42.F1 to */SLICE_42.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[2] (to jtaghub16_jtck)
                  --------
                    1.274   (81.6% logic, 18.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_66 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q1 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q1 to *b/SLICE_68.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.367 *b/SLICE_68.C1 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOFCO_D  ---     0.067 */SLICE_67.FCI to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.240 */SLICE_66.FCI to *b/SLICE_66.F0 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F0 to */SLICE_66.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOFCO_D  ---     0.067 */SLICE_39.FCI to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_41.FCI to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_40.FCI to *1/SLICE_40.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F0 to */SLICE_40.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q1 to *1/SLICE_37.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
C1TOFCO_DE  ---     0.367 *1/SLICE_37.A1 to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOFCO_D  ---     0.067 */SLICE_36.FCI to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q1 to *1/SLICE_39.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
C1TOFCO_DE  ---     0.367 *1/SLICE_39.A1 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOFCO_D  ---     0.067 */SLICE_38.FCI to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q1 to *1/SLICE_38.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
C1TOFCO_DE  ---     0.367 *1/SLICE_38.A1 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOFCO_D  ---     0.067 */SLICE_37.FCI to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_50.Q1 to *u/SLICE_50.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]
C1TOFCO_DE  ---     0.367 *u/SLICE_50.B1 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOFCO_D  ---     0.067 */SLICE_49.FCI to */SLICE_49.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_48.FCI to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay mg5ahub/SLICE_64 to mg5ahub/SLICE_67 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_64.CLK to *b/SLICE_64.Q1 mg5ahub/SLICE_64 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_64.Q1 to *b/SLICE_64.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.367 *b/SLICE_64.C1 to */SLICE_64.FCO mg5ahub/SLICE_64
ROUTE         1   e 0.001 */SLICE_64.FCO to */SLICE_68.FCI mg5ahub/rom_rd_addr_cry_0
FCITOFCO_D  ---     0.067 */SLICE_68.FCI to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF0_DE  ---     0.240 */SLICE_67.FCI to *b/SLICE_67.F0 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F0 to */SLICE_67.DI0 mg5ahub/rom_rd_addr_s_3 (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_65 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q1 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_67.Q1 to *b/SLICE_67.C1 mg5ahub/rom_rd_addr_4
C1TOFCO_DE  ---     0.367 *b/SLICE_67.C1 to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOFCO_D  ---     0.067 */SLICE_66.FCI to */SLICE_66.FCO mg5ahub/SLICE_66
ROUTE         1   e 0.001 */SLICE_66.FCO to */SLICE_65.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.240 */SLICE_65.FCI to *b/SLICE_65.F0 mg5ahub/SLICE_65
ROUTE         1   e 0.001 *b/SLICE_65.F0 to */SLICE_65.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_42.FCI to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_41.FCI to *1/SLICE_41.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F0 to */SLICE_41.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOFCO_D  ---     0.067 */SLICE_40.FCI to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF0_DE  ---     0.240 */SLICE_39.FCI to *1/SLICE_39.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F0 to */SLICE_39.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.349ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (1.272ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_51.CLK to *u/SLICE_51.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_51.Q1 to *u/SLICE_51.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_51.B1 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOFCO_D  ---     0.067 */SLICE_50.FCI to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_49.FCI to *u/SLICE_49.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F0 to */SLICE_49.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.272   (81.5% logic, 18.5% route), 4 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.291ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (1.065ns delay and 0.226ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_90.CLK to *u/SLICE_90.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_90.Q0 to *u/SLICE_90.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend
CTOF_DEL    ---     0.238 *u/SLICE_90.A1 to *u/SLICE_90.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90
ROUTE         1   e 0.232 *u/SLICE_90.F1 to *u/SLICE_90.CE Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59 (to jtaghub16_jtck)
                  --------
                    1.065   (56.4% logic, 43.6% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay mg5ahub/SLICE_64 to mg5ahub/SLICE_68 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_64.CLK to *b/SLICE_64.Q1 mg5ahub/SLICE_64 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_64.Q1 to *b/SLICE_64.C1 mg5ahub/rom_rd_addr_0
C1TOFCO_DE  ---     0.367 *b/SLICE_64.C1 to */SLICE_64.FCO mg5ahub/SLICE_64
ROUTE         1   e 0.001 */SLICE_64.FCO to */SLICE_68.FCI mg5ahub/rom_rd_addr_cry_0
FCITOF0_DE  ---     0.240 */SLICE_68.FCI to *b/SLICE_68.F0 mg5ahub/SLICE_68
ROUTE         1   e 0.001 *b/SLICE_68.F0 to */SLICE_68.DI0 mg5ahub/rom_rd_addr_s_1 (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
C1TOFCO_DE  ---     0.367 *1/SLICE_43.A1 to */SLICE_43.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 */SLICE_43.FCO to */SLICE_42.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[0]
FCITOF0_DE  ---     0.240 */SLICE_42.FCI to *1/SLICE_42.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 *1/SLICE_42.F0 to */SLICE_42.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[1] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q1 to *1/SLICE_37.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
C1TOFCO_DE  ---     0.367 *1/SLICE_37.A1 to */SLICE_37.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 */SLICE_37.FCO to */SLICE_36.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[12]
FCITOF0_DE  ---     0.240 */SLICE_36.FCI to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_67 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q1 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q1 to *b/SLICE_68.C1 mg5ahub/rom_rd_addr_2
C1TOFCO_DE  ---     0.367 *b/SLICE_68.C1 to */SLICE_68.FCO mg5ahub/SLICE_68
ROUTE         1   e 0.001 */SLICE_68.FCO to */SLICE_67.FCI mg5ahub/rom_rd_addr_cry_2
FCITOF0_DE  ---     0.240 */SLICE_67.FCI to *b/SLICE_67.F0 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F0 to */SLICE_67.DI0 mg5ahub/rom_rd_addr_s_3 (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_36.Q1 to *1/SLICE_36.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
C1TOFCO_DE  ---     0.367 *1/SLICE_36.A1 to */SLICE_36.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 */SLICE_36.FCO to */SLICE_35.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[14]
FCITOF0_DE  ---     0.240 */SLICE_35.FCI to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
C1TOFCO_DE  ---     0.367 *1/SLICE_41.A1 to */SLICE_41.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 */SLICE_41.FCO to */SLICE_40.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_40.FCI to *1/SLICE_40.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F0 to */SLICE_40.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q1 to *1/SLICE_38.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
C1TOFCO_DE  ---     0.367 *1/SLICE_38.A1 to */SLICE_38.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 */SLICE_38.FCO to */SLICE_37.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[10]
FCITOF0_DE  ---     0.240 */SLICE_37.FCI to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_50.Q1 to *u/SLICE_50.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]
C1TOFCO_DE  ---     0.367 *u/SLICE_50.B1 to */SLICE_50.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 */SLICE_50.FCO to */SLICE_49.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_49.FCI to *u/SLICE_49.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F0 to */SLICE_49.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
C1TOFCO_DE  ---     0.367 *1/SLICE_40.A1 to */SLICE_40.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 */SLICE_40.FCO to */SLICE_39.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[6]
FCITOF0_DE  ---     0.240 */SLICE_39.FCI to *1/SLICE_39.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F0 to */SLICE_39.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_51.CLK to *u/SLICE_51.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_51.Q1 to *u/SLICE_51.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]
C1TOFCO_DE  ---     0.367 *u/SLICE_51.B1 to */SLICE_51.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 */SLICE_51.FCO to */SLICE_50.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[0]
FCITOF0_DE  ---     0.240 */SLICE_50.FCI to *u/SLICE_50.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F0 to */SLICE_50.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[1] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_66 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q1 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_67.Q1 to *b/SLICE_67.C1 mg5ahub/rom_rd_addr_4
C1TOFCO_DE  ---     0.367 *b/SLICE_67.C1 to */SLICE_67.FCO mg5ahub/SLICE_67
ROUTE         1   e 0.001 */SLICE_67.FCO to */SLICE_66.FCI mg5ahub/rom_rd_addr_cry_4
FCITOF0_DE  ---     0.240 */SLICE_66.FCI to *b/SLICE_66.F0 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F0 to */SLICE_66.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay mg5ahub/SLICE_66 to mg5ahub/SLICE_65 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_66.CLK to *b/SLICE_66.Q1 mg5ahub/SLICE_66 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_66.Q1 to *b/SLICE_66.C1 mg5ahub/rom_rd_addr_6
C1TOFCO_DE  ---     0.367 *b/SLICE_66.C1 to */SLICE_66.FCO mg5ahub/SLICE_66
ROUTE         1   e 0.001 */SLICE_66.FCO to */SLICE_65.FCI mg5ahub/rom_rd_addr_cry_6
FCITOF0_DE  ---     0.240 */SLICE_65.FCI to *b/SLICE_65.F0 mg5ahub/SLICE_65
ROUTE         1   e 0.001 *b/SLICE_65.F0 to */SLICE_65.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_49.Q1 to *u/SLICE_49.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]
C1TOFCO_DE  ---     0.367 *u/SLICE_49.B1 to */SLICE_49.FCO Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 */SLICE_49.FCO to */SLICE_48.FCI Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_cry[4]
FCITOF0_DE  ---     0.240 */SLICE_48.FCI to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q1 to *1/SLICE_39.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
C1TOFCO_DE  ---     0.367 *1/SLICE_39.A1 to */SLICE_39.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 */SLICE_39.FCO to */SLICE_38.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[8]
FCITOF0_DE  ---     0.240 */SLICE_38.FCI to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.281ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (1.204ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
C1TOFCO_DE  ---     0.367 *1/SLICE_42.A1 to */SLICE_42.FCO Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 */SLICE_42.FCO to */SLICE_41.FCI Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_cry[2]
FCITOF0_DE  ---     0.240 */SLICE_41.FCI to *1/SLICE_41.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F0 to */SLICE_41.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[3] (to jtaghub16_jtck)
                  --------
                    1.204   (80.6% logic, 19.4% route), 3 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_195.CLK to */SLICE_195.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_195.Q0 to *a7_0_1_0.ADR9 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q1 to *a7_0_0_1.ADR6 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q0 to *a7_0_0_1.ADR7 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q1 to *a7_0_0_1.ADR8 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q0 to *a7_0_0_1.ADR5 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q0 to *a7_0_1_0.ADR5 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_193.CLK to */SLICE_193.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_193.Q1 to *a7_0_1_0.ADR6 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q0 to *a7_0_1_0.ADR7 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_194.CLK to */SLICE_194.Q1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_194.Q1 to *a7_0_1_0.ADR8 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.134ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1 (1.271ns delay and -0.137ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_195.CLK to */SLICE_195.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195 (from jtaghub16_jtck)
ROUTE         3   e 0.908 */SLICE_195.Q0 to *a7_0_0_1.ADR9 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4] (to jtaghub16_jtck)
                  --------
                    1.271   (28.6% logic, 71.4% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.072ns delay mg5ahub/SLICE_327 to mg5ahub/SLICE_327 (0.995ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_327.CLK to */SLICE_327.Q0 mg5ahub/SLICE_327 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_327.Q0 to */SLICE_327.B0 mg5ahub/bit_count_3
CTOOFX_DEL  ---     0.399 */SLICE_327.B0 to *LICE_327.OFX0 mg5ahub/SLICE_327
ROUTE         1   e 0.001 *LICE_327.OFX0 to *SLICE_327.DI0 mg5ahub/N_47_i (to jtaghub16_jtck)
                  --------
                    0.995   (76.6% logic, 23.4% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_67 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q0 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_67.Q0 to *b/SLICE_67.C0 mg5ahub/rom_rd_addr_3
CTOF1_DEL   ---     0.367 *b/SLICE_67.C0 to *b/SLICE_67.F1 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F1 to */SLICE_67.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF1_DEL   ---     0.367 *1/SLICE_39.A0 to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF1_DEL   ---     0.367 *1/SLICE_41.A0 to *1/SLICE_41.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F1 to */SLICE_41.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[4] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_36.Q0 to *1/SLICE_36.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF1_DEL   ---     0.367 *1/SLICE_36.A0 to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q0 to *1/SLICE_38.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF1_DEL   ---     0.367 *1/SLICE_38.A0 to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q0 to *1/SLICE_37.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF1_DEL   ---     0.367 *1/SLICE_37.A0 to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_50.Q0 to *u/SLICE_50.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]
CTOF1_DEL   ---     0.367 *u/SLICE_50.B0 to *u/SLICE_50.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F1 to */SLICE_50.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_49.Q0 to *u/SLICE_49.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]
CTOF1_DEL   ---     0.367 *u/SLICE_49.B0 to *u/SLICE_49.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F1 to */SLICE_49.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_68 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q0 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q0 to *b/SLICE_68.C0 mg5ahub/rom_rd_addr_1
CTOF1_DEL   ---     0.367 *b/SLICE_68.C0 to *b/SLICE_68.F1 mg5ahub/SLICE_68
ROUTE         1   e 0.001 *b/SLICE_68.F1 to */SLICE_68.DI1 mg5ahub/rom_rd_addr_s_2 (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF1_DEL   ---     0.367 *1/SLICE_42.A0 to *1/SLICE_42.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 *1/SLICE_42.F1 to */SLICE_42.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[2] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF1_DEL   ---     0.367 *1/SLICE_40.A0 to *1/SLICE_40.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F1 to */SLICE_40.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6] (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    1.040ns delay mg5ahub/SLICE_66 to mg5ahub/SLICE_66 (0.963ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_66.CLK to *b/SLICE_66.Q0 mg5ahub/SLICE_66 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_66.Q0 to *b/SLICE_66.C0 mg5ahub/rom_rd_addr_5
CTOF1_DEL   ---     0.367 *b/SLICE_66.C0 to *b/SLICE_66.F1 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F1 to */SLICE_66.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    0.963   (75.8% logic, 24.2% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_325 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q1 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         5   e 0.232 */SLICE_325.Q1 to */SLICE_325.B1 mg5ahub/bit_count_1
CTOF_DEL    ---     0.238 */SLICE_325.B1 to */SLICE_325.F1 mg5ahub/SLICE_325
ROUTE         1   e 0.001 */SLICE_325.F1 to *SLICE_325.DI1 mg5ahub/N_49_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.232 */SLICE_276.Q1 to */SLICE_276.C1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_276.C1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.232 */SLICE_276.Q0 to */SLICE_276.B0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_276.B0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.232 */SLICE_276.Q1 to */SLICE_276.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]
CTOF_DEL    ---     0.238 */SLICE_276.C0 to */SLICE_276.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F0 to *SLICE_276.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_36.Q1 to *1/SLICE_36.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]
CTOF_DEL    ---     0.238 *1/SLICE_36.A1 to *1/SLICE_36.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F1 to */SLICE_36.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q1 to *1/SLICE_37.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]
CTOF_DEL    ---     0.238 *1/SLICE_37.A1 to *1/SLICE_37.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F1 to */SLICE_37.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q1 to *1/SLICE_38.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]
CTOF_DEL    ---     0.238 *1/SLICE_38.A1 to *1/SLICE_38.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F1 to */SLICE_38.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_37.CLK to *1/SLICE_37.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_37.Q0 to *1/SLICE_37.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]
CTOF_DEL    ---     0.238 *1/SLICE_37.A0 to *1/SLICE_37.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37
ROUTE         1   e 0.001 *1/SLICE_37.F0 to */SLICE_37.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_38.CLK to *1/SLICE_38.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_38.Q0 to *1/SLICE_38.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]
CTOF_DEL    ---     0.238 *1/SLICE_38.A0 to *1/SLICE_38.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38
ROUTE         1   e 0.001 *1/SLICE_38.F0 to */SLICE_38.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q1 to *1/SLICE_39.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]
CTOF_DEL    ---     0.238 *1/SLICE_39.A1 to *1/SLICE_39.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F1 to */SLICE_39.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_35.CLK to *1/SLICE_35.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_35.Q0 to *1/SLICE_35.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]
CTOF_DEL    ---     0.238 *1/SLICE_35.A0 to *1/SLICE_35.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35
ROUTE         1   e 0.001 *1/SLICE_35.F0 to */SLICE_35.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_159.CLK to */SLICE_159.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_159.Q0 to */SLICE_159.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]
CTOF_DEL    ---     0.238 */SLICE_159.A1 to */SLICE_159.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159
ROUTE         1   e 0.001 */SLICE_159.F1 to *SLICE_159.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[13] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_39.CLK to *1/SLICE_39.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_39.Q0 to *1/SLICE_39.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]
CTOF_DEL    ---     0.238 *1/SLICE_39.A0 to *1/SLICE_39.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39
ROUTE         1   e 0.001 *1/SLICE_39.F0 to */SLICE_39.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q1 to *1/SLICE_40.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]
CTOF_DEL    ---     0.238 *1/SLICE_40.A1 to *1/SLICE_40.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F1 to */SLICE_40.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q1 to *1/SLICE_41.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]
CTOF_DEL    ---     0.238 *1/SLICE_41.A1 to *1/SLICE_41.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F1 to */SLICE_41.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[4] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q1 to *1/SLICE_42.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]
CTOF_DEL    ---     0.238 *1/SLICE_42.A1 to *1/SLICE_42.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 *1/SLICE_42.F1 to */SLICE_42.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[2] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_40.CLK to *1/SLICE_40.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_40.Q0 to *1/SLICE_40.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]
CTOF_DEL    ---     0.238 *1/SLICE_40.A0 to *1/SLICE_40.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40
ROUTE         1   e 0.001 *1/SLICE_40.F0 to */SLICE_40.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[5] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_41.CLK to *1/SLICE_41.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_41.Q0 to *1/SLICE_41.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]
CTOF_DEL    ---     0.238 *1/SLICE_41.A0 to *1/SLICE_41.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41
ROUTE         1   e 0.001 *1/SLICE_41.F0 to */SLICE_41.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[3] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_42.CLK to *1/SLICE_42.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_42.Q0 to *1/SLICE_42.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]
CTOF_DEL    ---     0.238 *1/SLICE_42.A0 to *1/SLICE_42.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42
ROUTE         1   e 0.001 *1/SLICE_42.F0 to */SLICE_42.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[1] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_49.Q1 to *u/SLICE_49.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]
CTOF_DEL    ---     0.238 *u/SLICE_49.B1 to *u/SLICE_49.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F1 to */SLICE_49.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_50.Q1 to *u/SLICE_50.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]
CTOF_DEL    ---     0.238 *u/SLICE_50.B1 to *u/SLICE_50.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F1 to */SLICE_50.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[2] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_111.CLK to */SLICE_111.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_111.Q0 to */SLICE_111.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]
CTOF_DEL    ---     0.238 */SLICE_111.D0 to */SLICE_111.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111
ROUTE         1   e 0.001 */SLICE_111.F0 to *SLICE_111.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_45_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_142.CLK to */SLICE_142.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_142.Q0 to */SLICE_142.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]
CTOF_DEL    ---     0.238 */SLICE_142.B1 to */SLICE_142.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142
ROUTE         1   e 0.001 */SLICE_142.F1 to *SLICE_142.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[3] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_161.CLK to */SLICE_161.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161 (from jtaghub16_jtck)
ROUTE        17   e 0.232 */SLICE_161.Q0 to */SLICE_161.C0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr
CTOF_DEL    ---     0.238 */SLICE_161.C0 to */SLICE_161.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161
ROUTE         1   e 0.001 */SLICE_161.F0 to *SLICE_161.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_306.CLK to */SLICE_306.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306 (from jtaghub16_jtck)
ROUTE         5   e 0.232 */SLICE_306.Q0 to */SLICE_306.C0 Test_reveal_coretop_instance/test_la0_inst_0/tt_prog_en_0
CTOF_DEL    ---     0.238 */SLICE_306.C0 to */SLICE_306.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306
ROUTE         1   e 0.001 */SLICE_306.F0 to *SLICE_306.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_end_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_43.CLK to *1/SLICE_43.Q1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_43.Q1 to *1/SLICE_43.A1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]
CTOF_DEL    ---     0.238 *1/SLICE_43.A1 to *1/SLICE_43.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43
ROUTE         1   e 0.001 *1/SLICE_43.F1 to */SLICE_43.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[0] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_48.CLK to *u/SLICE_48.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_48.Q0 to *u/SLICE_48.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]
CTOF_DEL    ---     0.238 *u/SLICE_48.B0 to *u/SLICE_48.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48
ROUTE         1   e 0.001 *u/SLICE_48.F0 to */SLICE_48.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_49.CLK to *u/SLICE_49.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *u/SLICE_49.Q0 to *u/SLICE_49.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]
CTOF_DEL    ---     0.238 *u/SLICE_49.B0 to *u/SLICE_49.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49
ROUTE         1   e 0.001 *u/SLICE_49.F0 to */SLICE_49.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[3] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_50.CLK to *u/SLICE_50.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_50.Q0 to *u/SLICE_50.B0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]
CTOF_DEL    ---     0.238 *u/SLICE_50.B0 to *u/SLICE_50.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50
ROUTE         1   e 0.001 *u/SLICE_50.F0 to */SLICE_50.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[1] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_105.CLK to */SLICE_105.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_105.Q0 to */SLICE_105.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker
CTOF_DEL    ---     0.238 */SLICE_105.D0 to */SLICE_105.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105
ROUTE         1   e 0.001 */SLICE_105.F0 to *SLICE_105.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_29_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_276.CLK to */SLICE_276.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276 (from jtaghub16_jtck)
ROUTE         7   e 0.232 */SLICE_276.Q0 to */SLICE_276.B1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]
CTOF_DEL    ---     0.238 */SLICE_276.B1 to */SLICE_276.F1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276
ROUTE         1   e 0.001 */SLICE_276.F1 to *SLICE_276.DI1 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_147.CLK to */SLICE_147.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_147.Q0 to */SLICE_147.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]
CTOF_DEL    ---     0.238 */SLICE_147.B1 to */SLICE_147.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147
ROUTE         1   e 0.001 */SLICE_147.F1 to *SLICE_147.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[13] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_145.CLK to */SLICE_145.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_145.Q0 to */SLICE_145.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]
CTOF_DEL    ---     0.238 */SLICE_145.B1 to */SLICE_145.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145
ROUTE         1   e 0.001 */SLICE_145.F1 to *SLICE_145.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[9] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_141.CLK to */SLICE_141.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141 (from jtaghub16_jtck)
ROUTE         5   e 0.232 */SLICE_141.Q0 to */SLICE_141.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]
CTOF_DEL    ---     0.238 */SLICE_141.B1 to */SLICE_141.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141
ROUTE         1   e 0.001 */SLICE_141.F1 to *SLICE_141.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[1] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_157.CLK to */SLICE_157.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_157.Q0 to */SLICE_157.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]
CTOF_DEL    ---     0.238 */SLICE_157.A1 to */SLICE_157.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157
ROUTE         1   e 0.001 */SLICE_157.F1 to *SLICE_157.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[9] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_155.CLK to */SLICE_155.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_155.Q0 to */SLICE_155.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]
CTOF_DEL    ---     0.238 */SLICE_155.A1 to */SLICE_155.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155
ROUTE         1   e 0.001 */SLICE_155.F1 to *SLICE_155.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[5] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_153.CLK to */SLICE_153.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_153.Q0 to */SLICE_153.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]
CTOF_DEL    ---     0.238 */SLICE_153.A1 to */SLICE_153.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153
ROUTE         1   e 0.001 */SLICE_153.F1 to *SLICE_153.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[1] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_162.CLK to */SLICE_162.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_162.Q0 to */SLICE_162.D0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en
CTOF_DEL    ---     0.238 */SLICE_162.D0 to */SLICE_162.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162
ROUTE         1   e 0.001 */SLICE_162.F0 to *SLICE_162.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en_3 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_326 to mg5ahub/SLICE_326 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_326.CLK to */SLICE_326.Q1 mg5ahub/SLICE_326 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_326.Q1 to */SLICE_326.A1 mg5ahub/bit_count_4
CTOF_DEL    ---     0.238 */SLICE_326.A1 to */SLICE_326.F1 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F1 to *SLICE_326.DI1 mg5ahub/N_46_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_68 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q0 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q0 to *b/SLICE_68.C0 mg5ahub/rom_rd_addr_1
CTOF_DEL    ---     0.238 *b/SLICE_68.C0 to *b/SLICE_68.F0 mg5ahub/SLICE_68
ROUTE         1   e 0.001 *b/SLICE_68.F0 to */SLICE_68.DI0 mg5ahub/rom_rd_addr_s_1 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_67 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q0 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_67.Q0 to *b/SLICE_67.C0 mg5ahub/rom_rd_addr_3
CTOF_DEL    ---     0.238 *b/SLICE_67.C0 to *b/SLICE_67.F0 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F0 to */SLICE_67.DI0 mg5ahub/rom_rd_addr_s_3 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_66 to mg5ahub/SLICE_66 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_66.CLK to *b/SLICE_66.Q0 mg5ahub/SLICE_66 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_66.Q0 to *b/SLICE_66.C0 mg5ahub/rom_rd_addr_5
CTOF_DEL    ---     0.238 *b/SLICE_66.C0 to *b/SLICE_66.F0 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F0 to */SLICE_66.DI0 mg5ahub/rom_rd_addr_s_5 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_287.CLK to */SLICE_287.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_287.Q0 to */SLICE_287.C0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_enz
CTOF_DEL    ---     0.238 */SLICE_287.C0 to */SLICE_287.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287
ROUTE         1   e 0.001 */SLICE_287.F0 to *SLICE_287.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_51.CLK to *u/SLICE_51.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51 (from jtaghub16_jtck)
ROUTE         4   e 0.232 *u/SLICE_51.Q1 to *u/SLICE_51.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]
CTOF_DEL    ---     0.238 *u/SLICE_51.B1 to *u/SLICE_51.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51
ROUTE         1   e 0.001 *u/SLICE_51.F1 to */SLICE_51.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[0] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_148.CLK to */SLICE_148.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_148.Q0 to */SLICE_148.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]
CTOF_DEL    ---     0.238 */SLICE_148.B1 to */SLICE_148.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148
ROUTE         1   e 0.001 */SLICE_148.F1 to *SLICE_148.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[15] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_146.CLK to */SLICE_146.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_146.Q0 to */SLICE_146.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]
CTOF_DEL    ---     0.238 */SLICE_146.B1 to */SLICE_146.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146
ROUTE         1   e 0.001 */SLICE_146.F1 to *SLICE_146.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[11] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_144.CLK to */SLICE_144.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_144.Q0 to */SLICE_144.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]
CTOF_DEL    ---     0.238 */SLICE_144.B1 to */SLICE_144.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144
ROUTE         1   e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[7] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_160.CLK to */SLICE_160.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_160.Q0 to */SLICE_160.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]
CTOF_DEL    ---     0.238 */SLICE_160.A1 to */SLICE_160.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160
ROUTE         1   e 0.001 */SLICE_160.F1 to *SLICE_160.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[15] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_158.CLK to */SLICE_158.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_158.Q0 to */SLICE_158.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]
CTOF_DEL    ---     0.238 */SLICE_158.A1 to */SLICE_158.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158
ROUTE         1   e 0.001 */SLICE_158.F1 to *SLICE_158.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[11] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_156.CLK to */SLICE_156.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_156.Q0 to */SLICE_156.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]
CTOF_DEL    ---     0.238 */SLICE_156.A1 to */SLICE_156.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156
ROUTE         1   e 0.001 */SLICE_156.F1 to *SLICE_156.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[7] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_154.CLK to */SLICE_154.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_154.Q0 to */SLICE_154.A1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]
CTOF_DEL    ---     0.238 */SLICE_154.A1 to */SLICE_154.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154
ROUTE         1   e 0.001 */SLICE_154.F1 to *SLICE_154.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[3] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_64 to mg5ahub/SLICE_64 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_64.CLK to *b/SLICE_64.Q1 mg5ahub/SLICE_64 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_64.Q1 to *b/SLICE_64.C1 mg5ahub/rom_rd_addr_0
CTOF_DEL    ---     0.238 *b/SLICE_64.C1 to *b/SLICE_64.F1 mg5ahub/SLICE_64
ROUTE         1   e 0.001 *b/SLICE_64.F1 to */SLICE_64.DI1 mg5ahub/rom_rd_addr_s_0 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_326 to mg5ahub/SLICE_326 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_326.CLK to */SLICE_326.Q0 mg5ahub/SLICE_326 (from jtaghub16_jtck)
ROUTE         4   e 0.232 */SLICE_326.Q0 to */SLICE_326.B0 mg5ahub/bit_count_2
CTOF_DEL    ---     0.238 */SLICE_326.B0 to */SLICE_326.F0 mg5ahub/SLICE_326
ROUTE         1   e 0.001 */SLICE_326.F0 to *SLICE_326.DI0 mg5ahub/N_48_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_68 to mg5ahub/SLICE_68 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_68.CLK to *b/SLICE_68.Q1 mg5ahub/SLICE_68 (from jtaghub16_jtck)
ROUTE         3   e 0.232 *b/SLICE_68.Q1 to *b/SLICE_68.C1 mg5ahub/rom_rd_addr_2
CTOF_DEL    ---     0.238 *b/SLICE_68.C1 to *b/SLICE_68.F1 mg5ahub/SLICE_68
ROUTE         1   e 0.001 *b/SLICE_68.F1 to */SLICE_68.DI1 mg5ahub/rom_rd_addr_s_2 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_325 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q0 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         6   e 0.232 */SLICE_325.Q0 to */SLICE_325.A0 mg5ahub/bit_count_0
CTOF_DEL    ---     0.238 */SLICE_325.A0 to */SLICE_325.F0 mg5ahub/SLICE_325
ROUTE         1   e 0.001 */SLICE_325.F0 to *SLICE_325.DI0 mg5ahub/bit_count_3_iv_0_m4_0 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_143.CLK to */SLICE_143.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_143.Q0 to */SLICE_143.B1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]
CTOF_DEL    ---     0.238 */SLICE_143.B1 to */SLICE_143.F1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143
ROUTE         1   e 0.001 */SLICE_143.F1 to *SLICE_143.DI1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[5] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_65 to mg5ahub/SLICE_65 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_65.CLK to *b/SLICE_65.Q0 mg5ahub/SLICE_65 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_65.Q0 to *b/SLICE_65.C0 mg5ahub/rom_rd_addr_7
CTOF_DEL    ---     0.238 *b/SLICE_65.C0 to *b/SLICE_65.F0 mg5ahub/SLICE_65
ROUTE         1   e 0.001 *b/SLICE_65.F0 to */SLICE_65.DI0 mg5ahub/rom_rd_addr_s_7 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_325 to mg5ahub/SLICE_325 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_325.CLK to */SLICE_325.Q0 mg5ahub/SLICE_325 (from jtaghub16_jtck)
ROUTE         6   e 0.232 */SLICE_325.Q0 to */SLICE_325.A1 mg5ahub/bit_count_0
CTOF_DEL    ---     0.238 */SLICE_325.A1 to */SLICE_325.F1 mg5ahub/SLICE_325
ROUTE         1   e 0.001 */SLICE_325.F1 to *SLICE_325.DI1 mg5ahub/N_49_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_67 to mg5ahub/SLICE_67 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_67.CLK to *b/SLICE_67.Q1 mg5ahub/SLICE_67 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_67.Q1 to *b/SLICE_67.C1 mg5ahub/rom_rd_addr_4
CTOF_DEL    ---     0.238 *b/SLICE_67.C1 to *b/SLICE_67.F1 mg5ahub/SLICE_67
ROUTE         1   e 0.001 *b/SLICE_67.F1 to */SLICE_67.DI1 mg5ahub/rom_rd_addr_s_4 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay mg5ahub/SLICE_66 to mg5ahub/SLICE_66 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_66.CLK to *b/SLICE_66.Q1 mg5ahub/SLICE_66 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *b/SLICE_66.Q1 to *b/SLICE_66.C1 mg5ahub/rom_rd_addr_6
CTOF_DEL    ---     0.238 *b/SLICE_66.C1 to *b/SLICE_66.F1 mg5ahub/SLICE_66
ROUTE         1   e 0.001 *b/SLICE_66.F1 to */SLICE_66.DI1 mg5ahub/rom_rd_addr_s_6 (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_75.CLK to *u/SLICE_75.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75 (from jtaghub16_jtck)
ROUTE         6   e 0.232 *u/SLICE_75.Q0 to *u/SLICE_75.C0 Test_reveal_coretop_instance/test_la0_inst_0/addr[5]
CTOF_DEL    ---     0.238 *u/SLICE_75.C0 to *u/SLICE_75.F0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75
ROUTE         1   e 0.001 *u/SLICE_75.F0 to */SLICE_75.DI0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_43_i (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.911ns delay Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 to Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (0.834ns delay and 0.077ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_36.CLK to *1/SLICE_36.Q0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *1/SLICE_36.Q0 to *1/SLICE_36.A0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]
CTOF_DEL    ---     0.238 *1/SLICE_36.A0 to *1/SLICE_36.F0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36
ROUTE         1   e 0.001 *1/SLICE_36.F0 to */SLICE_36.DI0 Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13] (to jtaghub16_jtck)
                  --------
                    0.834   (72.1% logic, 27.9% route), 2 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_336 to mg5ahub/SLICE_336 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_336.CLK to */SLICE_336.Q1 mg5ahub/SLICE_336 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_336.Q1 to */SLICE_336.M0 mg5ahub/er1_shift_reg_18 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_85.CLK to *u/SLICE_85.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85 (from jtaghub16_jtck)
ROUTE         1   e 0.232 *u/SLICE_85.Q0 to *u/SLICE_85.M1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_101 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_101 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_101.CLK to */SLICE_101.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_101 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_101.Q0 to */SLICE_101.M1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_109.CLK to */SLICE_109.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_109.Q1 to */SLICE_109.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_108.CLK to */SLICE_108.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_108.Q1 to */SLICE_108.M0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_93.CLK to *u/SLICE_93.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93 (from jtaghub16_jtck)
ROUTE        14   e 0.232 *u/SLICE_93.Q1 to *u/SLICE_93.M0 Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_100.CLK to */SLICE_100.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_100.Q0 to */SLICE_100.M1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_76.CLK to *u/SLICE_76.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76 (from jtaghub16_jtck)
ROUTE        24   e 0.232 *u/SLICE_76.Q1 to *u/SLICE_76.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[9] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_79.CLK to *u/SLICE_79.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79 (from jtaghub16_jtck)
ROUTE         5   e 0.232 *u/SLICE_79.Q1 to *u/SLICE_79.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[15] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_77.CLK to *u/SLICE_77.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77 (from jtaghub16_jtck)
ROUTE         6   e 0.232 *u/SLICE_77.Q1 to *u/SLICE_77.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[11] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_73.CLK to *u/SLICE_73.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73 (from jtaghub16_jtck)
ROUTE        19   e 0.232 *u/SLICE_73.Q1 to *u/SLICE_73.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[3] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_170 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_170 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_170.CLK to */SLICE_170.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_170 (from jtaghub16_jtck)
ROUTE         3   e 0.232 */SLICE_170.Q0 to */SLICE_170.M1 Test_reveal_coretop_instance/test_la0_inst_0/te_prog_din[0] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_330 to mg5ahub/SLICE_330 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_330.CLK to */SLICE_330.Q1 mg5ahub/SLICE_330 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_330.Q1 to */SLICE_330.M0 mg5ahub/er1_shift_reg_6 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_87 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_87 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_87.CLK to *u/SLICE_87.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_87 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *u/SLICE_87.Q0 to *u/SLICE_87.M1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_99.CLK to *u/SLICE_99.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99 (from jtaghub16_jtck)
ROUTE         2   e 0.232 *u/SLICE_99.Q0 to *u/SLICE_99.M1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_78.CLK to *u/SLICE_78.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78 (from jtaghub16_jtck)
ROUTE        20   e 0.232 *u/SLICE_78.Q1 to *u/SLICE_78.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[13] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_72.CLK to *u/SLICE_72.Q1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72 (from jtaghub16_jtck)
ROUTE        58   e 0.232 *u/SLICE_72.Q1 to *u/SLICE_72.M0 Test_reveal_coretop_instance/test_la0_inst_0/addr[1] (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 to Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_192.CLK to */SLICE_192.Q0 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_192.Q0 to */SLICE_192.M1 Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_329 to mg5ahub/SLICE_329 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_329.CLK to */SLICE_329.Q1 mg5ahub/SLICE_329 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_329.Q1 to */SLICE_329.M0 mg5ahub/er1_shift_reg_4 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_331 to mg5ahub/SLICE_331 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_331.CLK to */SLICE_331.Q1 mg5ahub/SLICE_331 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_331.Q1 to */SLICE_331.M0 mg5ahub/er1_shift_reg_8 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_333 to mg5ahub/SLICE_333 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_333.CLK to */SLICE_333.Q1 mg5ahub/SLICE_333 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_333.Q1 to */SLICE_333.M0 mg5ahub/er1_shift_reg_12 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_337 to mg5ahub/SLICE_337 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_337.CLK to */SLICE_337.Q1 mg5ahub/SLICE_337 (from jtaghub16_jtck)
ROUTE         2   e 0.232 */SLICE_337.Q1 to */SLICE_337.M0 mg5ahub/er1_shift_reg_20 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_332 to mg5ahub/SLICE_332 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_332.CLK to */SLICE_332.Q1 mg5ahub/SLICE_332 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_332.Q1 to */SLICE_332.M0 mg5ahub/er1_shift_reg_10 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_334 to mg5ahub/SLICE_334 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_334.CLK to */SLICE_334.Q1 mg5ahub/SLICE_334 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_334.Q1 to */SLICE_334.M0 mg5ahub/er1_shift_reg_14 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_335 to mg5ahub/SLICE_335 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_335.CLK to */SLICE_335.Q1 mg5ahub/SLICE_335 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_335.Q1 to */SLICE_335.M0 mg5ahub/er1_shift_reg_16 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay mg5ahub/SLICE_328 to mg5ahub/SLICE_328 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_328.CLK to */SLICE_328.Q1 mg5ahub/SLICE_328 (from jtaghub16_jtck)
ROUTE         1   e 0.232 */SLICE_328.Q1 to */SLICE_328.M0 mg5ahub/er1_shift_reg_2 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.

Unconstrained Preference:
   FREQUENCY NET "jtaghub16_jtck" 

Report:    0.746ns delay Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 to Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (0.595ns delay and 0.151ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 */SLICE_91.CLK to *u/SLICE_91.Q0 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91 (from jtaghub16_jtck)
ROUTE         9   e 0.232 *u/SLICE_91.Q0 to *u/SLICE_91.M1 Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1 (to jtaghub16_jtck)
                  --------
                    0.595   (61.0% logic, 39.0% route), 1 logic levels.


================================================================================
Preference: Unconstrained: INPUT_SETUP
            3 unconstrained paths found
--------------------------------------------------------------------------------

Unconstrained Preference:
   INPUT_SETUP PORT "ipButtons[0]" CLKPORT "ipClk" 

Report:    2.614ns delay ipButtons[0] to ipButtons[0]_MGIOL (1.721ns delay and 0.893ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813         52.PAD to       52.PADDI ipButtons[0]
ROUTE         1   e 0.908       52.PADDI to *s[0]_MGIOL.DI ipButtons_c[0] (to ipClk_c)
                  --------
                    1.721   (47.2% logic, 52.8% route), 1 logic levels.

Unconstrained Preference:
   INPUT_SETUP PORT "ipButtons[1]" CLKPORT "ipClk" 

Report:    2.614ns delay ipButtons[1] to ipButtons[1]_MGIOL (1.721ns delay and 0.893ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813         50.PAD to       50.PADDI ipButtons[1]
ROUTE         1   e 0.908       50.PADDI to *s[1]_MGIOL.DI ipButtons_c[1] (to ipClk_c)
                  --------
                    1.721   (47.2% logic, 52.8% route), 1 logic levels.

Unconstrained Preference:
   INPUT_SETUP PORT "ipButtons[2]" CLKPORT "ipClk" 

Report:    2.614ns delay ipButtons[2] to ipButtons[2]_MGIOL (1.721ns delay and 0.893ns setup)

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.813         53.PAD to       53.PADDI ipButtons[2]
ROUTE         1   e 0.908       53.PADDI to *s[2]_MGIOL.DI ipButtons_c[2] (to ipClk_c)
                  --------
                    1.721   (47.2% logic, 52.8% route), 1 logic levels.


================================================================================
Preference: Unconstrained: CLOCK_TO_OUT
            7 unconstrained paths found
--------------------------------------------------------------------------------

Unconstrained Preference:
   CLOCK_TO_OUT PORT "opLEDs[0]" CLKPORT "ipClk" 

Report:    2.388ns delay registers/SLICE_343 to opLEDs[0]

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_343.CLK to */SLICE_343.Q0 registers/SLICE_343 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_343.Q0 to       46.PADDO opLEDs_c[0]
DOPAD_DEL   ---     1.117       46.PADDO to         46.PAD opLEDs[0]
                  --------
                    2.388   (62.0% logic, 38.0% route), 2 logic levels.

Unconstrained Preference:
   CLOCK_TO_OUT PORT "opLEDs[1]" CLKPORT "ipClk" 

Report:    2.388ns delay registers/SLICE_343 to opLEDs[1]

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_343.CLK to */SLICE_343.Q1 registers/SLICE_343 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_343.Q1 to       45.PADDO opLEDs_c[1]
DOPAD_DEL   ---     1.117       45.PADDO to         45.PAD opLEDs[1]
                  --------
                    2.388   (62.0% logic, 38.0% route), 2 logic levels.

Unconstrained Preference:
   CLOCK_TO_OUT PORT "opLEDs[2]" CLKPORT "ipClk" 

Report:    2.388ns delay registers/SLICE_344 to opLEDs[2]

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_344.CLK to */SLICE_344.Q0 registers/SLICE_344 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_344.Q0 to       44.PADDO opLEDs_c[2]
DOPAD_DEL   ---     1.117       44.PADDO to         44.PAD opLEDs[2]
                  --------
                    2.388   (62.0% logic, 38.0% route), 2 logic levels.

Unconstrained Preference:
   CLOCK_TO_OUT PORT "opLEDs[3]" CLKPORT "ipClk" 

Report:    2.388ns delay registers/SLICE_344 to opLEDs[3]

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_344.CLK to */SLICE_344.Q1 registers/SLICE_344 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_344.Q1 to       43.PADDO opLEDs_c[3]
DOPAD_DEL   ---     1.117       43.PADDO to         43.PAD opLEDs[3]
                  --------
                    2.388   (62.0% logic, 38.0% route), 2 logic levels.

Unconstrained Preference:
   CLOCK_TO_OUT PORT "opLEDs[4]" CLKPORT "ipClk" 

Report:    2.388ns delay registers/SLICE_345 to opLEDs[4]

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_345.CLK to */SLICE_345.Q0 registers/SLICE_345 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_345.Q0 to       40.PADDO opLEDs_c[4]
DOPAD_DEL   ---     1.117       40.PADDO to         40.PAD opLEDs[4]
                  --------
                    2.388   (62.0% logic, 38.0% route), 2 logic levels.

Unconstrained Preference:
   CLOCK_TO_OUT PORT "opLEDs[5]" CLKPORT "ipClk" 

Report:    2.388ns delay registers/SLICE_345 to opLEDs[5]

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_345.CLK to */SLICE_345.Q1 registers/SLICE_345 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_345.Q1 to       39.PADDO opLEDs_c[5]
DOPAD_DEL   ---     1.117       39.PADDO to         39.PAD opLEDs[5]
                  --------
                    2.388   (62.0% logic, 38.0% route), 2 logic levels.

Unconstrained Preference:
   CLOCK_TO_OUT PORT "opLEDs[6]" CLKPORT "ipClk" 

Report:    2.388ns delay registers/SLICE_346 to opLEDs[6]

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.363 *SLICE_346.CLK to */SLICE_346.Q0 registers/SLICE_346 (from ipClk_c)
ROUTE         2   e 0.908 */SLICE_346.Q0 to       38.PADDO opLEDs_c[6]
DOPAD_DEL   ---     1.117       38.PADDO to         38.PAD opLEDs[6]
                  --------
                    2.388   (62.0% logic, 38.0% route), 2 logic levels.


================================================================================
Preference: Unconstrained: MAXDELAY
            0 unconstrained paths found
--------------------------------------------------------------------------------

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "ipClk" 50.000000 MHz ;  |   50.000 MHz|  138.370 MHz|   6  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 307 clocks:

Clock Domain: mg5ahub/rom_rd_addr_s_7   Source: mg5ahub/SLICE_65.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_6   Source: mg5ahub/SLICE_66.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_5   Source: mg5ahub/SLICE_66.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_4   Source: mg5ahub/SLICE_67.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_3   Source: mg5ahub/SLICE_67.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_2   Source: mg5ahub/SLICE_68.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_1   Source: mg5ahub/SLICE_68.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_0   Source: mg5ahub/SLICE_64.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/jce1   Source: mg5ahub/genblk0_genblk5_jtage_u.JCE1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/id_enable_0_sqmuxa   Source: mg5ahub/SLICE_741.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_9   Source: mg5ahub/SLICE_332.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_8   Source: mg5ahub/SLICE_331.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_7   Source: mg5ahub/SLICE_331.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_6   Source: mg5ahub/SLICE_330.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_5   Source: mg5ahub/SLICE_330.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_4   Source: mg5ahub/SLICE_329.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_3   Source: mg5ahub/SLICE_329.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_20   Source: mg5ahub/SLICE_337.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_2   Source: mg5ahub/SLICE_328.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_19   Source: mg5ahub/SLICE_337.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_18   Source: mg5ahub/SLICE_336.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_17   Source: mg5ahub/SLICE_336.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_16   Source: mg5ahub/SLICE_335.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_15   Source: mg5ahub/SLICE_335.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_14   Source: mg5ahub/SLICE_334.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_13   Source: mg5ahub/SLICE_334.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_12   Source: mg5ahub/SLICE_333.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_11   Source: mg5ahub/SLICE_333.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_10   Source: mg5ahub/SLICE_332.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/bit_count_3_iv_0_m4_0   Source: mg5ahub/SLICE_325.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_49_i   Source: mg5ahub/SLICE_325.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_48_i   Source: mg5ahub/SLICE_326.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_47_i   Source: mg5ahub/SLICE_327.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_46_i   Source: mg5ahub/SLICE_326.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_45_i   Source: mg5ahub/SLICE_742.F0   Loads: 10
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jupdate   Source: mg5ahub/genblk0_genblk5_jtage_u.JUPDATE   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jtdi   Source: mg5ahub/genblk0_genblk5_jtage_u.JTDI   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK   Loads: 181
   No transfer within this clock domain is found

Clock Domain: jtaghub16_jshift   Source: mg5ahub/genblk0_genblk5_jtage_u.JSHIFT   Loads: 55
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jrstn   Source: mg5ahub/genblk0_genblk5_jtage_u.JRSTN   Loads: 179
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jce2   Source: mg5ahub/genblk0_genblk5_jtage_u.JCE2   Loads: 18
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_ip_enable0   Source: SLICE_522.Q0   Loads: 63
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: ipClk_c   Source: ipClk.PAD   Loads: 252
   Covered under: FREQUENCY PORT "ipClk" 50.000000 MHz ;

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523.F0   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_end_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[42]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[41]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[40]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[39]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[38]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[37]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[36]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[35]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB17   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[34]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB16   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[33]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB15   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[32]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB14   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[31]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB13   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[30]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB12   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[29]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB11   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[28]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[27]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[26]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[25]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[24]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[23]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[22]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[21]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[20]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[19]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[18]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[17]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA17   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[16]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA16   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA15   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA14   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA13   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA12   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA11   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592.F1   Loads: 22
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191.Q0   Loads: 7
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/SLICE_730.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191.F1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/te_prog_din[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_170.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/parity_err   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163.Q0   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en_3   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538.F0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85.F1   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636.F1   Loads: 17
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_101.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91.Q1   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91.Q0   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_722.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_87.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_86.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560.F0   Loads: 28
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99.F1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_49_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_45_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_43_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_29_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93.Q1   Loads: 14
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/capture_dr   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85.F0   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr_15   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592.Q0   Loads: 26
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76.Q1   Loads: 24
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76.Q0   Loads: 19
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602.Q0   Loads: 21
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73.Q1   Loads: 19
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73.Q0   Loads: 34
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72.Q1   Loads: 58
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79.Q1   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78.Q1   Loads: 20
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78.Q0   Loads: 18
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77.Q1   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72.Q0   Loads: 55
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 3438 paths, 2 nets, and 4736 connections (96.06% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.0.240.2
Thu Jul 14 12:50:29 2022

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -u 0 -gt -mapchkpnt 0 -sethld -o ReadAnWrite_impl1.tw1 -gui ReadAnWrite_impl1_map.ncd ReadAnWrite_impl1.prf 
Design file:     readanwrite_impl1_map.ncd
Preference file: readanwrite_impl1.prf
Device,speed:    LFXP2-5E,M
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

Preference Summary

FREQUENCY PORT "ipClk" 50.000000 MHz (0 errors)
            3430 items scored, 0 timing errors detected.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers_Resetio" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets_UART_INST_opTxio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
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BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opTxWrEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/edgeDetector[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/reset" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opTxReady" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.SoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.EoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxSend" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData_tri_enable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opTxBusy" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxValid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/clockEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers_Resetio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets_UART_INST_opTxio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
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BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opTxWrEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/edgeDetector[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opTxReady" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.SoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.EoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxSend" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData_tri_enable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opTxBusy" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxValid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[9]" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/clockEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers_Resetio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[3]" (0 errors)
            1 item scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets_UART_INST_opTxio" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opTxWrEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/state[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/edgeDetector[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opTxReady" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Valid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.SoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.EoP" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxSend" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData_tri_enable" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txState[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/reset" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opTxBusy" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxValid" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[0]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[2]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[3]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[4]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[5]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[6]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[8]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[9]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/edgeDetector[1]" (0 errors)
            0 items scored.

BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/clockEnable" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets_UART_INST_edgeDetectorio[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets_UART_INST_edgeDetectorio[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers_Resetio" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers_Resetio" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readRegisters.Buttons_0io[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets_UART_INST_opTxio" TO PORT "opTx" (0 errors)
            1 item scored.

BLOCK PATH FROM CELL "uartPackets_UART_INST_opTxio" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/state[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/state[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opWrData_1[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opTxWrEnable" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/opTxWrEnable" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "writeController/dataLength[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/state[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/state[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Valid" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Valid" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Source[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Destination[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opTxStream.Data[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/opReadAddress[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/edgeDetector[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/edgeDetector[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/edgeDetector[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/edgeDetector[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "readController/dataLength[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[7]" TO PORT "opLEDs[7]" (0 errors)
            1 item scored.

BLOCK PATH FROM CELL "registers/opRdData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "registers/opRdData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/txState[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/rxState[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/reset" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/reset" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/receiveDataLength[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opTxReady" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opTxReady" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Valid" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Valid" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.SoP" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.SoP" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.EoP" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.EoP" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxSource[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxLength[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/localTxData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/locaTxDestination[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxSend" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxSend" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData_tri_enable" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData_tri_enable" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_TxData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txState[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txState[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/reset" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/reset" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opTxBusy" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opTxBusy" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxValid" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxValid" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[0]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[0]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[2]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[2]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[3]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[3]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[4]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[4]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[5]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[5]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[6]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[6]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[7]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[7]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[8]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[8]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[9]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[9]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/edgeDetector[1]" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/edgeDetector[1]" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/clockEnable" TO PORT "opTx" (0 errors)
            0 items scored.

BLOCK PATH FROM CELL "uartPackets/UART_INST/clockEnable" TO PORT "opLEDs[7]" (0 errors)
            0 items scored.

BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK JTAG PATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "ipClk" 50.000000 MHz ;
            3430 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.237ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              uartPackets/reset  (from ipClk_c +)
   Destination:    FF         Data in        uartPackets/UART_INST/reset  (to ipClk_c +)

   Delay:               0.223ns  (53.8% logic, 46.2% route), 1 logic levels.

 Constraint Details:

      0.223ns physical path delay uartPackets/SLICE_437 to uartPackets/SLICE_437 meets
     -0.014ns M_HLD and
      0.000ns delay constraint requirement (totaling -0.014ns) by 0.237ns

 Physical Path Details:

      Data path uartPackets/SLICE_437 to uartPackets/SLICE_437:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.120 *SLICE_437.CLK to */SLICE_437.Q0 uartPackets/SLICE_437 (from ipClk_c)
ROUTE        44   e 0.103 */SLICE_437.Q0 to */SLICE_437.M1 uartPackets/reset (to ipClk_c)
                  --------
                    0.223   (53.8% logic, 46.2% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers_Resetio" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipReset
   Destination:    FF         Data in        registers_Resetio  (to ipClk_c +)

   Delay:               0.807ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557         19.PAD to       19.PADDI ipReset
ROUTE         3   e 0.450       19.PADDI to *eset_MGIOL.DI ipReset_c (to ipClk_c)
                  --------
                    1.007   (55.3% logic, 44.7% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readRegisters.Buttons_0io[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets_UART_INST_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipReset
   Destination:    FF         Data in        Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]  (to ipClk_c +)

   Delay:               0.807ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557         19.PAD to       19.PADDI ipReset
ROUTE         3   e 0.450       19.PADDI to */SLICE_299.M1 ipReset_c (to ipClk_c)
                  --------
                    1.007   (55.3% logic, 44.7% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opWrData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/opTxWrEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "writeController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opTxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/opReadAddress[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/edgeDetector[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "readController/dataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opWrRegisters.LEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "registers/opRdData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/txState[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/rxState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/reset" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipReset
   Destination:    FF         Data in        uartPackets/reset  (to ipClk_c +)

   Delay:               0.807ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557         19.PAD to       19.PADDI ipReset
ROUTE         3   e 0.450       19.PADDI to */SLICE_437.M0 ipReset_c (to ipClk_c)
                  --------
                    1.007   (55.3% logic, 44.7% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/receiveDataLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opTxReady" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.SoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Length[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.EoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/opRxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxSource[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/locaTxDestination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData_tri_enable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/txBitCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/rxCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/opRxData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localTxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/localRxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipReset" TO CELL "uartPackets/UART_INST/clockEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipRx
   Destination:    FF         Data in        uartPackets_UART_INST_edgeDetectorio[0]  (to ipClk_c +)

   Delay:               0.807ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557        110.PAD to      110.PADDI ipRx
ROUTE         2   e 0.450      110.PADDI to  ipRx_MGIOL.DI ipRx_c (to ipClk_c)
                  --------
                    1.007   (55.3% logic, 44.7% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers_Resetio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readRegisters.Buttons_0io[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets_UART_INST_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opWrData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/opTxWrEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "writeController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opTxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/opReadAddress[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/edgeDetector[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "readController/dataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opWrRegisters.LEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "registers/opRdData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/txState[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/rxState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/receiveDataLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opTxReady" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.SoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Length[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.EoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/opRxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxSource[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/locaTxDestination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData_tri_enable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/txBitCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/rxCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/opRxData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localTxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/localRxData[9]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipRx
   Destination:    FF         Data in        uartPackets/UART_INST/localRxData[9]  (to ipClk_c +)

   Delay:               0.867ns  (48.0% logic, 52.0% route), 2 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557        110.PAD to      110.PADDI ipRx
ROUTE         2   e 0.450      110.PADDI to */SLICE_393.A1 ipRx_c
CTOF_DEL    ---     0.085 */SLICE_393.A1 to */SLICE_393.F1 uartPackets/UART_INST/SLICE_393
ROUTE         1   e 0.001 */SLICE_393.F1 to *SLICE_393.DI1 uartPackets/UART_INST/localRxData_5[9] (to ipClk_c)
                  --------
                    1.093   (58.7% logic, 41.3% route), 2 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipRx" TO CELL "uartPackets/UART_INST/clockEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets_UART_INST_edgeDetectorio[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers_Resetio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readRegisters.Buttons_0io[3]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         Port       Pad            ipButtons[3]
   Destination:    FF         Data in        readRegisters.Buttons_0io[3]  (to ipClk_c +)

   Delay:               0.807ns  (44.2% logic, 55.8% route), 1 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.557         54.PAD to       54.PADDI ipButtons[3]
ROUTE         1   e 0.450       54.PADDI to *s[3]_MGIOL.DI ipButtons_c[3] (to ipClk_c)
                  --------
                    1.007   (55.3% logic, 44.7% route), 1 logic levels.


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets_UART_INST_opTxio" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opWrData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/opTxWrEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "writeController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/state[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opTxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/opReadAddress[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/edgeDetector[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "readController/dataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opWrRegisters.LEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "registers/opRdData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/txState[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/rxState[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/receiveDataLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opTxReady" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Valid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Source[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.SoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Length[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.EoP" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Destination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/opRxStream.Data[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxSource[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxLength[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/locaTxDestination[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxSend" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData_tri_enable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_TxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txState[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/txBitCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/rxCounter[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/reset" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opTxBusy" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxValid" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/opRxData_1[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localTxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[0]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[2]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[3]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[4]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[5]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[6]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[8]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/localRxData[9]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/edgeDetector[1]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM PORT "ipButtons[3]" TO CELL "uartPackets/UART_INST/clockEnable" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets_UART_INST_edgeDetectorio[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets_UART_INST_edgeDetectorio[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers_Resetio" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers_Resetio" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readRegisters.Buttons_0io[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets_UART_INST_opTxio" TO PORT "opTx" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              uartPackets_UART_INST_opTxio  (from ipClk_c +)
   Destination:    Port       Pad            opTx

   Delay:               1.155ns  (61.0% logic, 39.0% route), 2 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
C2OUT_DEL   ---     0.199 opTx_MGIOL.CLK to *x_MGIOL.IOLDO opTx_MGIOL (from ipClk_c)
ROUTE         1   e 0.450 *x_MGIOL.IOLDO to      109.IOLDO opTx_c
DOPAD_DEL   ---     0.506      109.IOLDO to        109.PAD opTx
                  --------
                    1.155   (61.0% logic, 39.0% route), 2 logic levels.


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets_UART_INST_opTxio" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_stretch" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_ptr_reg[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_enbl[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_det_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trig_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[16]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[17]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[18]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[19]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[20]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[21]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[22]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[23]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[24]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[25]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[26]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[27]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[30]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[31]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[32]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[33]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[34]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[35]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[36]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[37]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[38]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[39]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[40]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[41]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout[42]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[16]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[17]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[18]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[19]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[20]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[21]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[22]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[23]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[24]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[25]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[26]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[27]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[30]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[31]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[32]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[33]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_din_d[34]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_wr_addr_cntr[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_d" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/start_bit" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/sample_en_d" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/rd_dout_tm_1[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cntr[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/pre_trig_cap_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/post_trig_cntr[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_pre_trig_frm[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/num_post_trig_frm[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/mem_full_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/last_addr_written[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full_reg" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/full" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/force_trig" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/clear" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/capture" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed_p1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/tm_u/armed" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_shift_en" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_prog_din[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/te_block" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[16]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[16]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[17]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[17]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[18]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[18]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[19]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[19]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[20]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[20]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[21]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[21]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[22]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[22]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[23]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[24]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[25]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[25]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[26]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[26]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[27]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[27]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[30]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[30]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[31]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[31]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[32]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[33]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[35]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[40]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[34]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[37]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[39]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[28]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[24]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[36]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[38]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[41]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout[42]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast_0[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_fast[29]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_29_rep1_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_28_rep1_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/r_w" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_checker" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_reclk[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d6" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_rep1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast_0" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1_fast" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jshift_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d3" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_reclk[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d5" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trigger_reg" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/trig_cnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg2[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg1[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0_read" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tcnt_0/reg0[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_en" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/trig_start_mask_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_out_reg" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_event_cnt_cntg_reg[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/state_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/num_then_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_shift[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/next_then_reg[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/jshift_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_start_d1" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_en" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/trig_start_mask_cnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[10]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[11]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[12]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[13]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[14]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_val[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt[15]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_out_reg" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_event_cnt_cntg_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/state_cntr[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/num_then_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/next_then_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/jshift_d2" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/tu_out" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/op_code[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/mask_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d2[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/input_a_d1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_1/compare_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/tu_out" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/op_code[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/mask_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d2[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/input_a_d1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "Test_reveal_coretop_instance/test_la0_inst_0/trig_u/tu_0/compare_reg[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/state[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/state[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opWrData_1[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opTxWrEnable" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/opTxWrEnable" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "writeController/dataLength[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/state[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/state[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Valid" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Valid" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Source[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Destination[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opTxStream.Data[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/opReadAddress[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/edgeDetector[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/edgeDetector[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/edgeDetector[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/edgeDetector[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "readController/dataLength[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opWrRegisters.LEDs[7]" TO PORT "opLEDs[7]" ;
            1 item scored.
--------------------------------------------------------------------------------


Blocked: 

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              registers/opWrRegisters.LEDs[7]  (from ipClk_c +)
   Destination:    Port       Pad            opLEDs[7]

   Delay:               1.200ns  (62.5% logic, 37.5% route), 2 logic levels.

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.122 *SLICE_346.CLK to */SLICE_346.Q1 registers/SLICE_346 (from ipClk_c)
ROUTE         2   e 0.450 */SLICE_346.Q1 to       37.PADDO opLEDs_c[7]
DOPAD_DEL   ---     0.630       37.PADDO to         37.PAD opLEDs[7]
                  --------
                    1.202   (62.6% logic, 37.4% route), 2 logic levels.


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "registers/opRdData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/txState[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/rxState[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/reset" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/reset" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/receiveDataLength[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opTxReady" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opTxReady" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Valid" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Valid" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Source[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.SoP" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.SoP" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Length[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.EoP" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.EoP" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Destination[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/opRxStream.Data[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxSource[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxLength[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/localTxData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/locaTxDestination[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxSend" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxSend" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData_tri_enable" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData_tri_enable" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_TxData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txState[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txState[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txCounter[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/txBitCounter[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/rxCounter[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/reset" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/reset" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opTxBusy" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opTxBusy" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxValid" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxValid" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/opRxData_1[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localTxData[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[0]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[0]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[2]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[2]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[3]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[3]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[4]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[4]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[5]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[5]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[6]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[6]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[7]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[7]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[8]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[8]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[9]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/localRxData[9]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/edgeDetector[1]" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/edgeDetector[1]" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/clockEnable" TO PORT "opTx" ;
            0 items scored.
--------------------------------------------------------------------------------


================================================================================
Preference: BLOCK PATH FROM CELL "uartPackets/UART_INST/clockEnable" TO PORT "opLEDs[7]" ;
            0 items scored.
--------------------------------------------------------------------------------

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "ipClk" 50.000000 MHz ;  |            -|            -|   1  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 307 clocks:

Clock Domain: mg5ahub/rom_rd_addr_s_7   Source: mg5ahub/SLICE_65.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_6   Source: mg5ahub/SLICE_66.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_5   Source: mg5ahub/SLICE_66.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_4   Source: mg5ahub/SLICE_67.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_3   Source: mg5ahub/SLICE_67.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_2   Source: mg5ahub/SLICE_68.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_1   Source: mg5ahub/SLICE_68.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/rom_rd_addr_s_0   Source: mg5ahub/SLICE_64.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/jce1   Source: mg5ahub/genblk0_genblk5_jtage_u.JCE1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/id_enable_0_sqmuxa   Source: mg5ahub/SLICE_741.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_9   Source: mg5ahub/SLICE_332.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_8   Source: mg5ahub/SLICE_331.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_7   Source: mg5ahub/SLICE_331.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_6   Source: mg5ahub/SLICE_330.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_5   Source: mg5ahub/SLICE_330.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_4   Source: mg5ahub/SLICE_329.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_3   Source: mg5ahub/SLICE_329.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_20   Source: mg5ahub/SLICE_337.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_2   Source: mg5ahub/SLICE_328.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_19   Source: mg5ahub/SLICE_337.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_18   Source: mg5ahub/SLICE_336.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_17   Source: mg5ahub/SLICE_336.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_16   Source: mg5ahub/SLICE_335.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_15   Source: mg5ahub/SLICE_335.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_14   Source: mg5ahub/SLICE_334.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_13   Source: mg5ahub/SLICE_334.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_12   Source: mg5ahub/SLICE_333.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_11   Source: mg5ahub/SLICE_333.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/er1_shift_reg_10   Source: mg5ahub/SLICE_332.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/bit_count_3_iv_0_m4_0   Source: mg5ahub/SLICE_325.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_49_i   Source: mg5ahub/SLICE_325.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_48_i   Source: mg5ahub/SLICE_326.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_47_i   Source: mg5ahub/SLICE_327.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_46_i   Source: mg5ahub/SLICE_326.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: mg5ahub/N_45_i   Source: mg5ahub/SLICE_742.F0   Loads: 10
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jupdate   Source: mg5ahub/genblk0_genblk5_jtage_u.JUPDATE   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jtdi   Source: mg5ahub/genblk0_genblk5_jtage_u.JTDI   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK   Loads: 181
   No transfer within this clock domain is found

Clock Domain: jtaghub16_jshift   Source: mg5ahub/genblk0_genblk5_jtage_u.JSHIFT   Loads: 55
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jrstn   Source: mg5ahub/genblk0_genblk5_jtage_u.JRSTN   Loads: 179
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_jce2   Source: mg5ahub/genblk0_genblk5_jtage_u.JCE2   Loads: 18
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: jtaghub16_ip_enable0   Source: SLICE_522.Q0   Loads: 63
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: ipClk_c   Source: ipClk.PAD   Loads: 252
   Covered under: FREQUENCY PORT "ipClk" 50.000000 MHz ;

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_wr_bit_cntr_1_sqmuxa_1   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_289.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/un1_tt_end_1   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_527.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_bit_cntr_1_sqmuxa_1_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_524.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_wr_addr_cntr_17[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_288.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_1_sqmuxa_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_525.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_prog_active_0_sqmuxa_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_286.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/tt_end_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_287.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_39.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_40.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_41.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_42.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_35.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_36.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_37.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_38.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/te_precnt_s[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_43.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/N_92_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_1/SLICE_523.F0   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/un1_tt_end_1   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_516.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_wr_addr_cntr_8[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_276.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_1_sqmuxa_1_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_515.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_prog_active_0_sqmuxa_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_274.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/tt_end_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_306.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnte   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_514.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_260.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_259.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_258.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_257.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_263.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_262.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_261.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/te_precnt_lm[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/trig_u/te_0/SLICE_256.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[42]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[41]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[40]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[39]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[38]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[37]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[36]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_1_0.DOA0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[35]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB17   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[34]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB16   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[33]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB15   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[32]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB14   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[31]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB13   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[30]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB12   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[29]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB11   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[28]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[27]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB9   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[26]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB8   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[25]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB7   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[24]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB6   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[23]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB5   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[22]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB4   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[21]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB3   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[20]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB2   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[19]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[18]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOB0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[17]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA17   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[16]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA16   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA15   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA14   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA13   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA12   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA11   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA10   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_int[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/pmi_ram_dpXbnonesadr4353243532p1329eca7_0_0_1.DOA0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/trace_dout_1_sqmuxa_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592.F1   Loads: 22
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_lm[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_195.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_194.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193.Q1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_rd_addr_cntr[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_193.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_192.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/tm_first_rd   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191.Q0   Loads: 7
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/scuba_vlo   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/genblk4.tr_mem/SLICE_730.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/N_9_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/tm_u/SLICE_191.F1   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/te_prog_din[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_170.Q0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/parity_err   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163.Q0   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/un1_jtdo_1_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_554.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_en_3   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_162.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_clr_5   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_161.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_157.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_156.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_155.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_154.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_160.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_159.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_158.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tt_crc_7[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_153.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnte   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_538.F0   Loads: 3
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_152.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_151.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_lm[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_150.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tr_dout_bit_cnt_8[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85.F1   Loads: 4
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_145.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_144.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_143.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_142.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_148.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_147.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_146.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/tm_crc_7[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_141.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_regce[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_636.F1   Loads: 17
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_122.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[7]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[6]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_121.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_120.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[42]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_139.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[41]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[40]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_138.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[39]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[38]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_137.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[37]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[36]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_136.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[35]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[33]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[32]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_134.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[31]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_119.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[28]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[27]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[26]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_131.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[25]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[24]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_130.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[23]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[22]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_129.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[21]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[20]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_128.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[19]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[18]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_127.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[17]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[16]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_126.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_124.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg_tr_dout_RNO[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_118.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[35]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[34]   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_628.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[33]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[32]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_109.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/shift_reg[23]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_108.Q1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_err_lat_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_718.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/parity_calc_5   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_104.OFX0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d5   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_101.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d4   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d3   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_100.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d2   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jupdate_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d2   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91.Q1   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/jce2_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_91.Q0   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/cmd_block_extend_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90.F0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_722.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d4   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_87.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d3   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_86.Q0   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d2   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85.Q1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/capture_dr_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85.Q0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnte   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_560.F0   Loads: 28
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_48.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_49.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_50.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/bit_cnt_s[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_51.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/addr_15_0_sqmuxa   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99.F1   Loads: 2
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_849   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_135.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_83   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_123.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_81   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_125.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_785   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_133.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_769   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_132.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_60_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_99.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_59   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_90.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_51   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_555.F0   Loads: 8
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_49_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_163.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_45_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_111.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_43_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_36   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_140.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_34_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_33_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_32_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_310.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_31_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_308.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_29_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_105.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_23_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1064_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_307.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1063_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1062_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_309.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1061_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1060_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_311.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1059_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1058_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_312.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1057_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1056_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_313.F1   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/N_1055_i   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_314.F0   Loads: 1
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/jshift_d1   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_93.Q1   Loads: 14
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/capture_dr   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_85.F0   Loads: 9
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr_15   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_592.Q0   Loads: 26
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[9]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76.Q1   Loads: 24
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[8]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_76.Q0   Loads: 19
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[5]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_75.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[4]   Source: Test_reveal_coretop_instance/test_la0_inst_0/SLICE_602.Q0   Loads: 21
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[3]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73.Q1   Loads: 19
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[2]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_73.Q0   Loads: 34
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[1]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72.Q1   Loads: 58
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[15]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79.Q1   Loads: 5
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[14]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_79.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[13]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78.Q1   Loads: 20
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[12]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_78.Q0   Loads: 18
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[11]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77.Q1   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[10]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_77.Q0   Loads: 6
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK

Clock Domain: Test_reveal_coretop_instance/test_la0_inst_0/addr[0]   Source: Test_reveal_coretop_instance/test_la0_inst_0/jtag_int_u/SLICE_72.Q0   Loads: 55
   No transfer within this clock domain is found

   Data transfers from:
   Clock Domain: jtaghub16_jtck   Source: mg5ahub/genblk0_genblk5_jtage_u.JTCK


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 3438 paths, 2 nets, and 4736 connections (96.06% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------